Intel CHIPSET 820E - Manual (Page 120)

Intel ® 820E Chipset
R
120 Design Guide
There are four pins which are used to put the Intel 82562ET/EM controller in different operating states:
Test_En, Isol_Tck, Isol_Ti, and Isol_Tex. The table below describes the operational/disable features for
this design.
Test_En Isol_Tck Isol_Ti Isol_Tex State
0 0 0 0 Enabled
0 1 1 1 Disabled w/ Clock (low power)
1 1 1 1 Disabled w/out Clock (lowest power)
The four control signals shown in the above table should be configured as follows: Test_En should be
pulled-down thru a 100
Ω resistor. The remaining 3 control signals should each be connected thru 100 Ω
series resistors to the common node “82652ET/EH_Disable” of the disable circuit.
2.22.6. Intel
®
82562ET and Intel
®
82562EH Components’ Dual-
Footprint Guidelines
These guidelines explain the proper layout for a dual-footprint solution. This configuration allows the
developer to install either the Intel
82562EH or Intel 82562ET/82562EM component, with only one
motherboard design. The following guidelines are for the Intel 82562ET/82562EH components’ dual-
footprint option. The guidelines called out in Sections 2.22.1 and 2.22.4 apply to this configuration. The
dual footprint for this particular solution uses a SSOP footprint for the Intel
82562ET component and a
TQFP footprint for the Intel 82562EH component. The combined footprint for this configuration is
shown in Figure 76 and Figure 77.
Figure 76. Dual-Footprint LAN Connect Interface
IO_subsys_dual_footprint_LAN_conn_IF
ICH
LAN_TXD[2:
LAN_RXD[2:
LAN_RSTSY
LAN_CL
L
8
2
5
6
2
E
T
S
S
O
P
Stub
Intel ®
82562EH
TQF