Intel CHIPSET 820E - Manual (Page 4)

Intel ® 820E Chipset
R
4 Design Guide
2.8.3. 2Ч/4Ч Timing Domain Routing Guidelines ...................................................62
2.8.4. AGP 2.0 Routing Summary .........................................................................64
2.8.5. AGP Clock Routing......................................................................................65
2.8.6. General AGP Routing Guidelines ................................................................65
2.8.6.1. Recommendations ..........................................................................65
2.8.7. V
DDQ
Generation and TYPEDET#................................................................66
2.8.8. V
REF
Generation for AGP 2.0 (2× and 4×)....................................................68
2.8.9. Compensation..............................................................................................70
2.8.10. AGP Pull-Ups...............................................................................................70
2.8.10.1. AGP Signal Voltage Tolerance List.................................................71
2.8.11. Motherboard / Add-in Card Interoperability..................................................71
2.8.12. AGP Universal Retention Mechanism (RM) ................................................72
2.9. Hub Interface .................................................................................................................74
2.9.1. 8-Bit Hub Interface Routing Guidelines .......................................................75
2.9.1.1. 8-Bit Hub Interface Data Signals.....................................................75
2.9.1.2. 8-Bit Hub Interface Strobe Signals..................................................75
2.9.1.3. 8-Bit Hub Interface HUBREF Generation/Distribution.....................75
2.9.1.4. 8-Bit Hub Interface Compensation..................................................77
2.9.1.5. 8-Bit Hub Interface Decoupling Guidelines .....................................77
2.10. System Bus Design – Pentium ® III Processor for the Intel ® PGA370 Socket Layout
Guidelines ......................................................................................................................77
2.10.1. System Bus Ground Plane Reference.........................................................78
2.11. Additional Host Bus Guidelines......................................................................................78
2.12. IDE Interface ..................................................................................................................79
2.12.1. Cable Detection for Ultra ATA/66 and Ultra ATA/100..................................80
2.12.2. Combination Host-Side/Device-Side Cable Detection.................................80
2.12.3. Device-Side Cable Detection .......................................................................82
2.12.4. Primary IDE Connector Requirements ........................................................83
2.12.5. Secondary IDE Connector Requirements....................................................84
2.13. AC’97 .............................................................................................................................85
2.13.1. AC’97 Audio Codec Detect Circuit and Configuration Options ....................86
2.13.2. Communication and Networking Riser (CNR) .............................................90
2.13.3. AC’97 Routing..............................................................................................91
2.13.4. Motherboard Implementation.......................................................................92
2.14. USB................................................................................................................................92
2.14.1. Using Native USB Interface .........................................................................92
2.14.3. Disabling the Native USB Interface of ICH2 ................................................93
2.15. ISA Support....................................................................................................................93
2.16. I/O APIC Design Recommendation ...............................................................................94
2.17. SMBus/SMLink Interface ...............................................................................................94
2.18. PCI .................................................................................................................................96
2.19. RTC................................................................................................................................96
2.19.1. RTC Crystal .................................................................................................97
2.19.2. External Capacitors .....................................................................................97
2.19.3. RTC Layout Considerations.........................................................................98
2.19.4. RTC External Battery Connection................................................................98
2.19.5. RTC External RTCRST Circuit ....................................................................99
2.19.6. RTC Routing Guidelines ............................................................................100
2.19.7. VBIAS DC Voltage and Noise Measurements...........................................100
2.19.8. RTC-Well Input Strap Requirements .........................................................100
2.20. SPKR Pin Consideration..............................................................................................100
2.21. ICH2 PIRQ Routing......................................................................................................101