Intel CHIPSET 820E - Manual (Page 235)

3-20-2000_10:15
39
RAMBUS TERMINATION
11
TERM_ROW[2:0]
TERM_ROW1 TERM_ROW0 TERM_ROW2
11
TERM_DQB[8:0]
TERM_DQB0 TERM_DQB2 TERM_DQB3 TERM_DQB4 TERM_DQB5 TERM_DQB6 TERM_DQB7 TERM_DQB8 TERM_DQB1
11
TERM_COL[4:0]
TERM_COL3 TERM_COL2 TERM_COL0 TERM_COL1 TERM_COL4
11
TERM_DQA[8:0]
TERM_DQA8 TERM_DQA3 TERM_DQA2 TERM_DQA1 TERM_DQA6 TERM_DQA5 TERM_DQA4 TERM_DQA0 TERM_DQA7
11
TERM_SCK TERM_CMD
11
C280 0.1UF
C278 0.1UF
C281 0.1UF
C282 0.1UF
0.1UF C283
0.1UF C273
0.1UF C275
0.1UF C274
0.1UF C276
0.1UF C279
0.1UF C271
C269 0.1UF
C277 0.1UF
90.9-1%
R291
90.9-1%
R293
R290
39.2-1%
R292
39.2-1%
R277
28-1%
R279
28-1% 28-1%
R280
28-1%
R283
28-1%
R282
28-1%
R285 R284
28-1%
R268
28-1%
R267
28-1%
R266
28-1% 28-1%
R265
28-1%
R264
28-1%
R263
28-1%
R262 R261
28-1%
R260
28-1%
R275
28-1%
R274
28-1%
R276
28-1%
R269
28-1% 28-1%
R271
28-1%
R270 R278
28-1%
R281
28-1% 28-1%
R272
28-1%
R273
DRAWN BY: LAST REVISED:
SHEET:
FOLSOM, CALIFORNIA 95630 1900 PRAIRIE CITY ROAD
87
6
5
4
3
2
1
A B C D
1
2
3
4
5
6
7
8
D C B A
PCG PLATFORM DESIGN
REV:
0.5
PROJECT:
OF 40
TITLE: INTEL(R) 820E CHIPSET 2 DIMM FCPGA REFERENCE BOARD
R
PCG AE
Camino2
VCC1_8
VCC1_8
Rambus
* Termination
NOTE :
per two RSL signals. Use one 0.1uF cap