Intel CHIPSET 820E - Manual (Page 124)

Intel ® 820E Chipset
R
124 Design Guide
2.23. FWH Flash BIOS Guidelines
The general compatibility guidelines and the design recommendations for supporting the FWH Flash
BIOS device are discussed next. Most changes will be incorporated into the BIOS. Refer to the FWH
Flash BIOS specification or equivalent.
2.23.1. In-Circuit FWH Flash BIOS Programming
All cycles destined for the FWH Flash BIOS appear on PCI. The ICH2 hub interface-to-PCI bridge puts
all processor boot cycles out on the PCI (before sending them out on the FWH Flash BIOS interface). If
the ICH2 is set for subtractive decode, these boot cycles can be accepted by a positive-decode agent out
on the PCI. This enables booting from a PCI card that positively decodes these memory cycles. To boot
from a PCI card, it is necessary to keep the ICH2 in the subtractive-decode mode. If a PCI boot card is
inserted and the ICH2 is programmed for positive decode, two devices will positively decode the same
cycle. In systems with a PCI-to-ISA bridge, it also is necessary to keep the NOGO signal asserted when
booting from a PCI ROM. Note that it is not possible to boot from a ROM behind a PCI-to-ISA bridge.
After booting from the PCI card, it is possible to program the FWH Flash BIOS in circuit and program
the ICH2 CMOS.
2.23.2. FWH Flash BIOS VPP Design Guidelines
The VPP pin on the FWH Flash BIOS is used for programming the flash cells. The FWH Flash BIOS
supports a VPP of 3.3 V or 12 V. If VPP is 12 V, the flash cells will program about 50% faster than at
3.3 V. However, the FWH Flash BIOS only supports 12 V VPP for 80 hours. The 12 V VPP is useful in
a programmer environment, which is typically an event that occurs very infrequently (much less than 80
hours). The VPP pin must be tied to 3.3 V on the motherboard.