Intel CHIPSET 820E - Manual (Page 112)

Intel ® 820E Chipset
R
112 Design Guide
2.22.3. Intel
®
82562EH Home/PNA* Guidelines
Table 24. Related Documents
Title Doc #
Intel ® 82562EH HomePNA 1-Mbit/s Physical Layer Interface Product
Preview Datasheet
OR-2183
RS-82562EH 1-Mbit/s Home PNA LAN Connect Option Application
Note OR-2182
For correct LAN performance, designers must follow the general guidelines outlined in Section 2.22.2.
Additional guidelines for implementing an Intel
82562EH Home/PNA* LAN connect component are
provided in the following sections.
2.22.3.1. Power and Ground Connections
Power and ground connection rules include the following:
• For optimal performance, place decoupling capacitors on the backside of the PCB, directly under
the Intel
82562EH component, with equal distance from both pins of the capacitor to power/ground.
The analog power supply pins for the Intel 82562EH (V
CCA
, V
SSA
) should be isolated from the digital V
CC
and V
SS
through the use of ferrite beads. In addition, adequate filtering and decoupling capacitors should
be provided between V
CC
and V
SS
as well as V
CCA
and V
SSA
power supplies.
2.22.3.2. Guidelines for Intel ® 82562EH Component Placement
Component placement can affect the signal quality, emissions, and temperature of a board design. This
section discusses guidelines for component placement.
Careful component placement provides the following benefits:
• Decreases potential problems directly related to electromagnetic interference (EMI), which could
result in failure to meet FCC specifications
• Simplifies the task of routing traces. To some extent, component orientation affects the trace routing
complexity. The overall objective is to minimize turns and crossovers between traces.
It is important to minimize the space needed for the HomePNA LAN interface because all other
interfaces will compete for physical space on a motherboard near the connector edge. As with most
subsystems, the HomePNA LAN circuits must be as close as possible to the connector. Thus, all designs
must be optimized to fit in a very small space.
2.22.3.3. Crystals and Oscillators
To minimize the effects of EMI, clock sources should not be placed near I/O ports or board edges.
Radiation from these devices may be coupled onto the I/O ports or out of the system chassis. Crystals
should also be kept away from the HomePNA magnetics module, to prevent communication interference.
The crystal’s retaining straps (if they exist) should be grounded to prevent possible radiation from the
crystal case, and the crystal should lie flat against the PC board, to provide better coupling of the
electromagnetic fields to the board.