Document Outline

• DIO 6533 User Manual
  • Warranty
  • Copyright
  • Trademarks
  • MEDICAL WARNING
• Table of Contents
• About This Manual
  • Organization of This Manual
  • Conventions Used in This Manual
  • National Instruments Documentation
  • Related Documentation
  • Customer Communication
• Chapter 1 Introduction
  • About the DIO 6533 Devices
  • Using PXI with CompactPCI
  • What You Need to Get Started
  • Software Programming Choices
    • National Instruments Application Software
    • NI-DAQ Driver Software
    • Register-Level Programming
  • Optional Equipment
  • Unpacking
• Chapter 2 Installation and Configuration
  • Software Installation
  • Hardware Installation
    • Installing the PCI-DIO-32HS
    • Installing the PXI-6533
    • Installing the AT-DIO-32HS
    • Installing the DAQCard-6533
  • PCI, PXI, and DAQCard Device Configuration
  • AT Device Configuration
    • Bus Interface
      • Plug and Play Mode
      • Switchless Data Acquisition
• Chapter 3 Hardware Overview
  • Unstrobed I/O
  • Strobed I/O—Pattern Generation and Handshaking
    • Pattern and Change Detection
      • Pattern-Detection Triggers
      • Change Detection
      • Message Generation
    • Handshaking Protocols
      • 8255 Emulation
      • Level ACK
      • LeadingEdge Pulse
      • Long Pulse
      • TrailingEdge Pulse
      • Burst Mode
    • Comparing Protocols
    • Starting a Handshaking Transfer
      • Controlling the Startup Sequence
      • Controlling Line Polarities
  • Transfer Rates
• Chapter 4 Signal Connections
  • I/O Connector
    • Signal Descriptions
      • Signal Characteristics
      • Control Signal Summary
    • RTSI Bus Interface
      • Board and RTSI Clocks
      • RTSI Triggers
  • Data Signal Connections
    • Unstrobed I/O
    • Strobed I/O
  • Timing Connections
  • Pull-Up and Pull-Down Connections
  • Power Connections
  • Field Wiring and Termination
• Chapter 5 Signal Timing
  • Pattern-Generation Timing
    • Request Timing
      • Internal Requests
      • External Requests
    • Trigger Timing
  • Handshake Timing
    • 8255 Emulation
      • Input
      • Output
      • 8255 Emulation Mode Timing Specifications
    • Other Asynchronous Modes
      • LevelACK Mode
      • LeadingEdge Mode
      • LongPulse Mode
      • TrailingEdge Mode
    • Burst Mode
      • Burst Mode Timing Specifications
• Appebdix A Specifications
  • PCI-DIO-32HS, PXI-6533, AT-DIO-32HS, and DAQCard-6533 Devices
    • Digital I/O
    • Strobed I/O
      • Pattern Generation
      • Handshaking
    • Pattern and Change Detection
    • Triggers
      • Start and Stop Triggers
      • RTSI Triggers (PCI, PXI, AT)
    • Bus Interfaces
    • Power Requirement
    • Physical
    • Environment
• Appendix B Optional Adapter Description
• Appendix C Customer Communication
• Glossary
• Index
• Figures
  • Figure 11. The Relationship Between the Programmi...
  • Figure 21. DAQCard-6533 Completed Installation
  • Figure 31. PCIDIO32HS/PXI-6533 Block Diagram
  • Figure 32. ATDIO-32HS Block Diagram
  • Figure 33. DAQCard-6533 Block Diagram
  • Figure 34. Pattern Detection Example
  • Figure 41. 6533 Device I/O Connector Pin Assignme...
  • Figure 42. RTSI Bus Signal Connection
  • Figure 43. Example of Data Signal Connections
  • Figure 44. Transmission Line Terminations
  • Figure 51. Pattern-Generation Timing
  • Figure 52. Internal Request Timing
  • Figure 53. External Request Timing
  • Figure 54. Trigger Input Signal Timing
  • Figure 55. 8255 Emulation Mode Input
  • Figure 56. 8255 Emulation Mode Output
  • Figure 57. 8255 Emulation Timing
  • Figure 58. LevelACK Mode Input
  • Figure 59. LevelACK Mode Output
  • Figure 510. LevelACK Mode Input Timing
  • Figure 511. LevelACK Mode Output Timing
  • Figure 512. LeadingEdge Mode Input
  • Figure 513. LeadingEdge Mode Output
  • Figure 514. LeadingEdge Mode Input Timing
  • Figure 515. LeadingEdge Mode Output Timing
  • Figure 516. Long-Pulse Mode Input
  • Figure 517. Long-Pulse Mode Output
  • Figure 518. LongPulse Mode Input Timing
  • Figure 519. LongPulse Mode Output Timing
  • Figure 520. TrailingEdge Mode Input
  • Figure 521. TrailingEdge Mode Output
  • Figure 522. TrailingEdge Mode Input Timing
  • Figure 523. TrailingEdge Mode Output Timing
  • Figure 524. Input Burst Mode Transfer Example
  • Figure 525. Output Burst Mode Transfer Example
  • Figure 526. Burst Mode Output Timing (Default)
  • Figure 527. Burst Mode Input Timing (Default)
  • Figure 528. Burst Mode Output Timing (PCLK Revers...
  • Figure 529. Burst Mode Input Timing (PCLK Reverse...
  • Figure B1. 68-to-50-Pin Adapter Pin Assignments
• Tables
  • Table 11. Pins Used by the PXI6533 Device
  • Table 21. PC AT I/O Address Map (Continued)
  • Table 22. PC AT Interrupt Assignment Map (Continu...
  • Table 23. PC AT 16Bit DMA Channel Assignment Map...
  • Table 31. 6533 Handshaking Protocols
  • Table 41. Signal Descriptions (Continued)
  • Table 42. Control Signal Summary