National Instruments DIO 6533 - Manual (Page 92)

Chapter 5 Signal Timing
© National Instruments Corporation 5-33 DIO 6533 User Manual
Figure 5-29. Burst Mode Input Timing (PCLK Reversed)
Parameter Description Minimum Maximum
Input Parameters
t
pc PCLK cycle time
50 —
t
pw
PCLK high pulse duration 20 —
t
pl
PCLK low pulse duration 20 —
t
rs
Setup time from REQ valid to PCLK falling
edge 1 —
t
rh
Hold time from PCLK to REQ invalid 0 —
Output Parameters
t
pa
PCLK to ACK valid — 22
t
ah
Hold time from PCLK to ACK invalid 3 —
All timing values are in nanoseconds.
PCLK
ACK
Data In
REQ
tdis tdih
trs
tpa
tpw tpl
tpc
trh
tah