National Instruments DIO 6533 - Manual (Page 38)

Chapter 3 Hardware Overview
© National Instruments Corporation 3-9 DIO 6533 User Manual
expected from the peripheral device. One protocol, burst mode, also
uses PCLK signals.
The following sections describe the handshaking protocols offered by
the 6533 devices. Refer to
Table 3-1 for further information on these
protocols. For timing details, see Chapter 5, Signal Timing .
8255 Emulation
The 8255 emulation protocol emulates the strobed protocols obeyed by
the 8255 and 82C55 PPI chips—chips that are used, for example, on the
National Instruments PC-DIO-24 and PC-DIO-96/PnP. Because of
faster response times, a wider data path, and FIFO buffering, 8255
emulation mode offers much higher data transfer rates than an actual
8255 chip. The 8255 emulation protocol offers the highest peak transfer
rate of any protocol except burst mode.
Level ACK
After each transfer, the 6533 device asserts the ACK signal to the
peripheral device. Holding the ACK line at the asserted level, the
6533 device does not begin a new transfer until a false-to-true transition
on the REQ line from the peripheral device occurs.
Leading-Edge Pulse
After each transfer, the 6533 device sends a pulse on the ACK line to
the peripheral device. The 6533 device then waits for a false-to-true
transition on the REQ line, the start of a REQ pulse, before starting a
new transfer. You can specify an ACK pulse delay.
Long Pulse
Long-pulse mode is the same as leading-edge pulse mode, except that
you can specify a minimum pulse width, instead of an ACK pulse delay.
Trailing-Edge Pulse
After each transfer, the 6533 device sends a pulse on the ACK line to
the peripheral device. The 6533 device waits for a true-to-false
transition on the REQ line, the end of a REQ pulse, before starting a
new transfer.