2 function block diagram, Function block diagram – MITSUBISHI ELECTRIC 700 Series User Manual

Page 52

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47

System Configuration

2

CC-

L

in

k CO

M

M

UNICAT

ION

2.1.2

Function block diagram

How I/O data are transferred to/from the inverter in CC-Link will be described using
function blocks.
(1) Between the master station and inverter in the CC-Link system, link refresh is

always made at 3.5 to 18ms (512 points).

(2) I/O refresh and master station's sequence program are executed asynchronously.
(3) Data read from the inverter are read from the buffer memory of the CC-Link

system master/local module using the FROM instruction.

(4) Data to be written to the inverter are written to the buffer memory of the CC-Link

system master/local module using the TO instruction.

1)

I/O signals assigned to the CC-Link system master/local module. These signals
are used to make communication between the PLC CPU and CC-Link system
master/local module.

2)

Input data from the inverter can be read, and output data from the inverter can be
written. Buffer memory read/write is performed using the FROM/TO instruction of
the sequence program. Refer to page 57 for details of the buffer memory.

3)

PLC link start is commanded from the sequence program. After PLC link has
started, link refresh is always made asynchronously with the sequence program
execution.

4)

I/O data are transferred between the CC-Link system master/local module and
inverter CPU via the sequence program.

5)

I/O data are transferred between the inverter CPU and sequence program. (5)
indicates the operation performed when CC-Link is not used, and is irrelevant to
1) to 4).)

REMARKS

Programs cannot be read/written via CC-Link communication.

CPU

Inverter

CC-Link module

4)

P

LC CP

U

1) CC-Link module
I/O signals

2) Buffer memory
read/write

In

te

rf

ac

e

wi

th

PL

C

Buffer
memory

C

C

-L

in

k in

te

rf

ac

e

3) CC-Link
dedicated
cable

C

C

-L

in

k in

te

rf

a

ce

B

ui

lt-

in

s

equ

en

ce

pr

og

ra

m

5)

I/O

data

In

ve

rt

er

CPU

Input signal

Output signal

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