Mitsubishi Motors DS5000TK - Manual (Page 114)

USER’S GUIDE
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was originally written into bit position D8. During the final
shift register operation, another 0 is shifted in from the
left so that the Transmit Shift register contains all 0’s.
Also at this time, the Transmit Interrupt flag (TI) is set
and a serial interrupt will be generated if enabled.
During serial data transmission in Mode 0, SHCLK is ini-
tially driven low onto the TXD pin at S3 of the machine
cycle when D0 is output. During the time that the data
word is shifted out, SHCLK will be low during S3, S4,
and S5 and high during S6, S1, and S2 of every machine
cycle.
A serial data word will be shifted into the Receive Shift
register as soon as the condition REN=1 and RI=0 is sa-
tisfied. This condition can only be initiated by a write to
the SCON register from the application software. At
S6P2 of the second machine cycle following the write to
SCON, the RXD pin will be sampled and the value (D0)
will be shifted into the MSB position of the Receive Shift
register. Seven more shifts will occur at S6P2 of subse-
quent machine cycles until the entire 8–bit word has
been shifted into the Receive Shift register.
The SHCLK signal will be initially output low on the TXD
pin starting at S3P1 of the same machine cycle in which
D0 was sampled. As in the case described above for
transmit, SHCLK will be low during S3, S4, and S5 and
high during S6, S1, and S2 of every machine cycle.
After the last data bit (D7) has been shifted in, the control
logic will immediately load the Receive Data Buffer at
the SBUF register address with the contents of the Re-
ceive Shift register. At S1P1 of the 10th machine cycle
following the write to SCON which initiated reception,
the Receive Interrupt flag will be set and a serial inter-
rupt will be generated if it has been enabled.