Mitsubishi Motors DS5000TK - Manual (Page 60)

USER’S GUIDE
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SECTION 7: POWER MANAGEMENT
Introduction
All Dallas Semiconductor microcontrollers are imple-
mented using fully static CMOS circuitry for low power
consumption. Power consumption is a linear function of
crystal frequency. Two software initiated modes are
available for further power saving at times when proces-
sing is not required and V
CC
is at normal operating volt-
age. These are the Idle and Stop modes. The additional
third mode is the Data Retention or Zero Power State
which is made possible by the on–chip, circuitry. The
control and status bits which apply to these operating
modes are contained in the PCON register and are sum-
marized in Figure 7–1. In addition, Table 7–1 summa-
rizes the state of external pins in each of these modes.
Idle Mode
The Idle mode suspends activity of the CPU. However,
the on–chip I/O function, including the timer/counters,
and serial port continue their operation. This greatly re-
duces the number of switching nodes and thereby dra-
matically reduces the total power consumption of the
device. The Idle mode is useful for applications in which
lower power consumption is desired with fast response
to external interrupts but no other processing.
Software can invoke the Idle mode by setting the IDL bit
in the PCON register (PCON.0) to a logic 1 as shown in
Figure 7–1. The instruction which sets this bit will be the
last instruction executed before Idle mode operation be-
gins. Once in the Idle mode, the microprocessor pre-
serves the entire CPU status including the Stack Point-
er, Program Counter, Program Status Word,
Accumulator, and RAM. There are two ways to termi-
nate the Idle mode. The first is from an interrupt which
has been previously enabled prior to entering Idle
mode. This will clear the IDL bit in the PCON register
and will cause the CPU to enter the interrupt service rou-
tine as normal. When the RETI instruction is executed,
the next instruction which will be executed is the one
which immediately follows the instruction that set the
IDL bit.
The second method of terminating the Idle mode is by a
Reset. At this time the IDL bit is cleared and the CPU is
placed in the reset state. Since the clock oscillator con-
tinues to run in the Idle mode, an oscillator start up delay
(referred to as t
POR
in the AC Electrical Specifications)
will not be generated following the reset. Two machine
cycles are required to complete the reset operation (24
oscillator periods). It should be noted that the Watchdog
Timer continues to run during Idle and that a reset from
the on–chip Watchdog Timer will terminate Idle mode.
CONTROL/STATUS BITS FOR POWER CONTROL Figure 7–1
Bit Description:
PCON.6: POR
“Power On Reset” Indicates that the previous reset was initiated during a Power On sequence.
Initialization: Cleared to a 0 when a Power On Reset occurs. Remains at 0 until it is set to a
1 by software.
Read Access: Can be read normally at any time.
Write Access: Can be written only by using the Timed Access register.
PCON.5: PFW
“Power Fail Warning” Indicates that a potential power failure is in progress. Set to a 1 when V
CC
voltage is below the V
PFW
threshold. Cleared to a 0 immediately following a
read of the PCON register. Once set, it will remain set until read regardless
of V
CC
.
Initialization: Cleared to a 0 during a Power–On Reset.
Read Access: Can be read normally at any time.