Mitsubishi Motors DS5000TK - Manual (Page 117)

USER’S GUIDE
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ware. In an overrun condition with RI=1, the originally re-
ceived word will remain in the Receive Data Buffer and
all successively received data words will be lost.
When SM2=1, received data words will be selectively
discarded in a manner depending on the asynchronous
mode selected.
The operational details which are unique to each of the
asynchronous modes are summarized below.
Mode 1
In Mode 1, the asynchronous serial data word is ten bits
long, including one start bit, eight data bits, and one stop
bit. The baud rate generation is derived from the Timer 1
overflow output and is therefore programmable.
Figure 14–3 is a functional block diagram of the opera-
tion of the serial I/O port in Mode 1 operation including
the timing waveform.
In Mode 1 operation, the SM2 bit may be used to discard
a received serial data word in which a “framing error” is
detected, i.e., when a valid stop bit has not been de-
tected. When SM2=1. the incoming serial data word will
be ignored unless the received Stop bit=1. If SM2=0,
then the value of the received Stop bit will be loaded into
the RB8 status flag so that it may be processed by the
application software.
Mode 2 and 3
In Mode 2 and 3, the asynchronous serial data word is
11 bits long, including one start bit, eight data bits, a pro-
grammable 9th data bit, and one stop bit. For Mode 2,
the Baud Rate Generator clock is programmable to ei-
ther 1/32 or 1/64 of the clock oscillator frequency (f
CLK
),
depending on the state of the SMOD bit (PCON.7) as
follows:
f
CLK
64
f
CLK
32
SMOD BRG CLOCK
0
1
For Mode operation, the baud rate generator clock is the
Timer 1 Overflow output as described for Mode 1.
Transmission and reception takes place for Modes 2
and 3 as described except as noted below.
When the Transmit Shift register is written in Mode 2, the
register is simultaneously written with a 0 in bit position
D0 for a Start bit and a 1 is written into D10 for a Stop bit.
D9 is the programmable bit which is written with the
state of TB8 (SCON.3). TB8 can be written with the val-
ue of 1 or 0 by the application software.
On receive, the eight data bits are shifted into the Re-
ceive Shift register following the detection of a valid
Start bit. After the Stop bit has been detected, the Re-
ceive Data Buffer will be loaded with the contents of the
Receive Shift register if RI=0 and SM2=0. Also at this
time, the programmable 9th data bit will be loaded into
RB8 in the SCON register. If RI=1 after the time the Stop
bit is sample, then the incoming word will be lost.
The SM2 flag may be used in the implementation of a
multiprocessor communication scheme by selectively
discarding incoming serial data words according to the
state of the programmable 9th data bit. When SM2=1,
only those words in which this 9th bit is a 1 will be loaded
into the Receive Data Buffer and cause a serial interrupt
to be generated. Thus, the programmable 9th bit can be
used to flag an incoming data character as an address
field as opposed to a data field, for example.