Mitsubishi Motors DS5000TK - Manual (Page 63)

USER’S GUIDE
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Power Fail Interrupt
When V
CC
is stable, program execution proceeds as
normal. If V
CC
should decay from its nominal operating
voltage and drop to a level below the V
PFW
threshold,
then the internal PFW status flag (PCON.5) will be set.
In addition, a Power Fail Warning interrupt will be gener-
ated if it has been enabled via the EPFW control bit
(PCON.3). The purpose of these indicators is to warn
the processor of a potential power failure.
The V
PFW
threshold is above the specified minimum
value for V
CC
(V
CCmin
) for full processor operation. The
V
PFW
threshold is selected so that with a reasonable
power supply slew rate, ample time is allowed for the ap-
plication software to save all critical information which
would otherwise be lost in the absence of V
CC
. Such in-
formation may include the states of the Accumulator,
Stack Pointer, Data Pointer, and other Special Function
registers which are initialized with a reset when V
CC
voltage is applied once again. Saved data can be
placed into Scratchpad RAM or Byte–wide NV RAM.
Through the use of the Power Fail Warning interrupt, an
orderly shutdown of the system may be performed prior
to the time that processor operation is halted in the
event that V
CC
voltage is removed entirely.
The PFW flag is set to a logic 1 whenever the V
CC
level
is below the V
PFW
threshold. It is cleared in one of two
ways: 1) a read of the PFW bit from software, or 2) a
Power On Reset. If V
CC
is still below the V
PFW
threshold
when the bit is cleared, then the PFW bit will be immedi-
ately set once again. An interrupt will be generated any
time that both the EPFW bit and the PFW flag are set.
Total Power Failure
If V
CC
voltage should fall below the V
CCmin
threshold,
processor operation will halt. This is done by first placing
the CPU in a reset condition and then stopping the inter-
nal clock oscillator circuit, as illustrated in Figure 7–2. At
this time the interface to the Program/Data RAM is dis-
abled by pulling the CE line high. This action guarantees
an orderly shutdown for the lithium-backed RAM.
The microprocessor is automatically placed in the Data
Retention state, if V
CC
voltage drops below V
LI
, the con-
trol circuitry accomplishes this by switching the internal
power supply line (V
CCI
) from pin to the lithium power
source. At this time, data is retained and no power is
drawn from V
CC
.
When power is once again applied to the system, the
V
CC
voltage will eventually cross the V
LI
threshold.
When this action is detected, the microprocessor will
automatically switch its internal supply line from the lithi-
um source back to the V
CC
pin. When V
CC
voltage
eventually goes above the V
CCmin
threshold, the clock
oscillator is allowed to start up and an internal Power On
Reset cycle is executed. Part of the cycle involves a
considerable delay that is generated to allow the clock
oscillator frequency to stabilize. Activity on the RST pin
is ignored until this sequence is completed. The time re-
quired for this cycle is shown as t
POR
in Figure 7–2 and
is specified in the AC Electrical Specifications. A de-
tailed description of the Power On reset cycle operation
is given in Section 10.
Typically, the time taken for the Power On Reset cycle
will be longer to complete than it takes for V
CC
to rise
above the V
PFW
threshold. In this case the internal PFW
flag will be reset before execution of the user’s program
begins as illustrated in Figure 7–2. If the Power On Re-
set cycle completes before V
CC
>V
PFW
, then PFW will
be set again as a result of V
CC
<V
PFW
during user soft-
ware execution. A Power Fail Interrupt will occur at this
time if the EPFW bit is enabled. A user should monitor
the POR bit to know the power supply status. Refer to
Figure 7–3 for details.
Partial Power Failures
Two cases of partial power failure can occur in which
V
CC
voltage does not go through a completed power fail
cycle as described above. The first case is that in which
V
CC
drops below the V
CCmin
threshold and then returns
to its nominal level without going below the V
LI
thresh-
old. The second case is that in which V
CC
drops below
the V
PFW
threshold and then returns to its nominal level
without going below the V
CCmin
threshold. Both of these
cases are very possible in a system application and
could be caused by a “brownout” condition on an AC
power line.
The first case is indistinguishable by the software from
the complete power fail cycle which was previously de-
scribed. When V
CC
drops below V
PFW
the PFW flag will
be set and the clock oscillator will be stopped when V
CC
drops below V
CCmin
. The only operational difference is
that if V
CC
never drops below the V
LI
threshold, the in-
ternal power supply line will never be switched over to
the lithium cell. When V
CC
rises back above the V
CCmin