Mitsubishi Motors DS5000TK - Manual (Page 116)

USER’S GUIDE
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ASYNCHRONOUS OPERATION
Mode 1, 2, and 3 provide asynchronous, full-duplex
communication via the Serial I/O Port. The serial data
word is either 10 or 11 bits long, depending on the mode
selected. All three modes include one start bit, eight
data bits, and one stop bit. Modes 2 and 3 include an
additional, programmable 9th data bit. TXD is used for
serial data output, while RXD is used for serial data in-
put. In all three modes, the serial data word is both trans-
mitted and received LSB first. The baud rate generator
clock pulse (BRG clock) is derived either from the Timer
1 overflow output or divided directly from the clock oscil-
lator frequency (of period t
CLK
). The following descrip-
tion applies to all three of the operational modes.
Figure 14–3 is a functional block diagram of the opera-
tion of the serial I/O port in Mode 1 including the timing
waveforms which should be referred to in the discussion
below.
Asynchronous serial data output begins whenever soft-
ware writes to the SBUF register. When the write opera-
tion occurs at the time indicated by the WRSBUF signal
in the timing diagram, the contents of the 8–bit data bus
will be loaded into bits D8–D1 of the Transmit Shift regis-
ter. Simultaneously, a 0 will be loaded into the D0 bit
position of the shift register and a 1 will be loaded into
the Stop bit position. (D9 for Mode 1, D10 for Modes
2 or 3).
During data transmission, the clocking frequency pro-
vided by the output of Timer 1 is divided down by a factor
of 16 by the hardware to establish the serial output bit
rate. Following the write operation to the Transmit Shift
register, the LSB will be shifted out to the output latch of
the TXD pin at the next time the divide–by–16 counter
rolls over to zero. This counter is not synchronized to the
machine cycles associated with instruction execution.
As a result, data transmission will commence anywhere
from 0 to 16 of the Baud Rate Generator clocks from the
time that the Transmit Shift register is written. Succes-
sive bits from the Transmit Shift register will be shifted
into the output latch of the TXD pin each time the
divide–by–16 counter rolls over to zero. As each shift
right operation is performed, a 0 is shifted into the MSB
position from the left. When the Stop bit is shifted into the
latch, the shifting operation is complete and the TI flag
will be set. A serial interrupt will be generated if it has
been enabled.
The Baud Rate Generator clock output is fed directly
into the Bit Detector to perform serial data reception.
Reception begins when a valid start bit of 0 is detected
on the RXD pin. The Bit Detector will determine when
this has occurred as follows: On each BRG clock pulse,
the RXD pin will be sampled for a 1–to–0 transition.
When such a transition is recognized, the Bit Detector
will then reset its own internal divide–by–16 counter and
sample the RXD pin on the 7th, 8th, and 9th BRG clock
times following the transition. If a logic 0 level is detected
on two out of these three sample times, a valid start bit is
assumed. Otherwise, the Bit Detector will reject the in-
coming signal as a start bit and will repeat the process
by searching for another 1–to–0 transition on RXD.
If a valid start bit is detected, the RXD pin will be
sampled in the middle of each successive bit time until
the entire 10–bit or 11–bit serial word has been re-
ceived. Following the detection of a valid start bit,
successive bit times begin each time that the Bit Detec-
tor’s divide–by–16 counter rolls over to 0. During each
bit time, the RXD pin is sampled on the 7th, 8th, and 9th
BRG clock times. For the data bits, the logic level which
is read at least two out of the three sample times by the
Bit Detector will be the one which is shifted into the Re-
ceive Shift register. Just after the logic level is detected
during the 10th bit time, the control logic will test to see if
the following conditions are true:
a) The previous state of RI was 0.
b) SM2=0; or if SM2=1, then if the 10th received
bit=1.
If these conditions are met during the 10th bit time, then
the control logic will not perform another shift, but will
instead load the contents of the Receive Shift register
into the Receive Data Buffer, load the logic state deter-
mined at the Stop bit time into the RB8 status flag (if
SM2=0), and set the RI bit. A serial interrupt will then be
generated if it the appropriate enable bits have been set.
If the above conditions are not satisfied during the stop
bit time, then the received word is lost.
The first condition is interpreted by the control logic to
mean an “overrun” condition has been detected. This
means that a serial data word has been received before
software read the previous word from the Receive Data
Buffer. Only a hardware reset or writing logic 0 to the RI
bit will clear RI. It is therefore recommended that soft-
ware clear the RI bit after reading from the SBUF regis-
ter. This signals the hardware that a properly received
data word has been processed by the application soft-