Mitsubishi Motors DS5000TK - Manual (Page 17)

USER’S GUIDE
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MCON.3: RA32/8
“Range Address”: Sets the maximum usable address on the Byte–wide bus.
RA32/8 = 0 sets Range Address = 1FFFH (8K); RA32/8 = 1 sets Range Ad-
dress = 7FFFH (32K)
Initialization: Set to a 1 on a No V
LI
Power On Reset and when the Security Lock bit (SL) is
cleared to a 0 from a previous 1 state. Remains unchanged on all other types
of resets.
Read Access: May be read normally anytime.
Write Access: Cannot be modified by the application software; can only be written during
Program Load mode.
MCON.2: ECE2
“Enable Chip Enable 2”: Used to enable or disable the CE2 signal to additional RAM Data Memory
space. This bit should always be cleared to 0 in the DS5000–8, DS5000–32,
DS2250–8, and DS2250–32 versions.
Initialization: Cleared to 0 only during a No V
LI
Power On Reset.
Read Access: Read normally anytime.
Write Access: Can be written normally anytime.
MCON.1: PAA
“Partition Address Access”: Used to protect the programming of the Partition Address select bits. PA3–0
cannot be written when PAA=0. PAA can be written only via the Timed Ac-
cess register.
Initialization: PAA is cleared on a reset.
Read Access: PAA may be read anytime.
Write Access: The Timed Access register must be used to perform any type of write opera-
tion on the PAA bit.
DS5001/DS5002 Memory Organization
As mentioned above, the DS5001/DS5002 series con-
sists of the DS5001FP chip, the DS2251T module, the
DS5002FP chip, and the DS2252T module. Note that the
DS5002FP is a high security version of the DS5001FP,
but has the same memory map and I/O. The program-
ming model discussed in this section applies to all of
these parts and any reference to the DS5001 applies to
all of them. The DS5001 series Byte–wide bus has 16
address lines, eight data lines, a R/W strobe, and a total
of eight chip enables to access nonvolatile RAM and pe-
ripherals. Chip enables include CE1 – CE4 and PE1 –
PE4. The four chip enables (CE1–4) are for nonvolatile
RAM access. How they are connected depends on the
memory mode and the selection of SRAMs. The PE sig-
nals are generally for memory mapped peripherals, but
can be used for more RAM if desired. PE1 and PE2 are
lithium–backed, PE3 and PE4 are not. In the case of a
module, PE1 may be connected to a real–time clock.
Memory map control resides in the MCON (C6h) and
RPCTL (D8h) registers. The MCON register has se-
lected differences from its DS5000 counterpart. These
are documented below. The RPCTL is not present in the
DS5000. Also, not all of the bits in this register pertain to
memory map control. This section describes the rele-
vant bits and the SFR section below documents the en-
tire register.
The DS5001 series can use multiple 8K x 8 or 32K x 8
SRAMs or a single 128K x 8 SRAM. These parts can op-
erate in either a Partitionable (like DS5000) or non–
partitionable mode. The mode is selected via the PM
(MCON.1) bit of the MCON register. Note, the DS5001
MCON provides different functions than the DS5000. In