Mitsubishi Motors DS5000TK - Manual (Page 126)

USER’S GUIDE
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BYTE–WIDE RAM INSTRUCTION EXECUTION TIMING Figure 15–3
S1
P1 P2
S2
P1 P2
S3
P1 P2
S4
P1 P2
S5
P1 P2
S6
P1 P2
S1
P1 P2
S2
P1 P2
S3
P1 P2
S4
P1 P2
S5
P1 P2
S6
P1 P2
S1
P1 P2
OPCODE
FETCH
NEXT OPCODE
FETCH (DISCARD)
NEXT OPCODE
FETCH
OPCODE
FETCH
READ 2ND
BYTE (OPERAND)
NEXT OPCODE
FETCH
OPCODE
FETCH
NEXT OPCODE
FETCH (DISCARD) NEXT OPCODE
FETCH
OPCODE
FETCH
NO FETCH
CYCLE
NEXT OPCODE
FETCH
DATA MEMORY
READ OR WRITE
XTAL2
ALE
A) 1–BYTE, 1–CYCLE INSTRUCTION (E.G., DEC A)
B) 2–BYTE, 1–CYCLE INSTRUCTION (E.G., MOV A, #DATA)
C) 1–BYTE, 2–CYCLE INSTRUCTION (E.G., INC DPTR)
D) MOVX: 1–BYTE, 2–CYCLE INSTRUCTION
EXPANDED PROGRAM MEMORY TIMING
A Program Memory access will occur on the Expanded
Bus any time that instructions are executed from Pro-
gram Memory space which is mapped outside of the
Byte–wide RAM. Mapping of Program Memory on the
Expanded Bus is dependent on the programming of the
Partition, Range, the state of the external EA pin, and
the internal Security Lock. Refer to Section 4 for a de-
tailed discussion on Program Memory mapping.
The external timing for the Expanded Program Memory
fetch cycle is illustrated in Figure 15–4. A full 16–bit ad-
dress is always output on the multiplexed Expanded
Bus (P2, P0) pins whenever such an access is per-
formed. The high–order eight bits will be output on the
P2 pins while the low–order eight bits will be output on
the P0 pins. Strong pull–ups are enabled onto Ports 0
and 2 for the duration of time that 1’s are output on the
port for address bits. As long as Program Memory is be-
ing executed from the Expanded Bus, P0 and P2 pins
are unavailable for use as general–purpose I/O.