Mitsubishi Motors DS5000TK - Manual (Page 68)

USER’S GUIDE
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During subsequent program execution, the Watchdog
Timer can be reset by a Timed Access write operation
which sets the RWT bit to a 1. This will cause the Watch-
dog Timer to begin counting machine cycles again from
an initial count of 0. The RWT bit itself is automatically
cleared immediately after the Watchdog Timer is reset.
An instruction sequence which performs this operation
is as follows.
This code allows the reset of the Watchdog Timer:
MOV 0C7H, #0AAH ; 1st TA Value
MOV 0C7H, #055H ; 2nd TA Value
SETB IP.7 ; Reset Watchdog Timer
If the timeout period is ever reached without the timer
being reset by the software, the Watchdog Timer will re-
set the CPU, set the WTR status flag, and will begin
counting again. The WTR flag allows the application
software to distinguish this type of reset from other pos-
sible sources so that special processing can be per-
formed to accommodate this case. This flag will be set in
response to a timeout, regardless of whether the reset is
enabled. The WTR bit is cleared only by a read of the
PCON register. Therefore, this register should be read
during initialization following a reset in order to properly
interpret the source of the reset.
The Watchdog Timer Reset Bit (WTR) is held in a logic 1
state for 8192 clock cycles following the time–out of the
watchdog 122,880 cycle counter. During this time, the
bit may be read but attempts to clear the bit will fail. This
condition will not be noticed if the Enable Watchdog
Timer bit (EWT) is set, because the 8192 cycle count will
be reset during the device reset triggered by the watch-
dog time–out. The bit may then be cleared, if desired,
during application’s power–on reset routine.
Some applications may use the watchdog timer but not
set the EWT bit, preferring instead to poll the WTR bit in
software to detect a watchdog time–out. In this case,
one approach is for the application software to continu-
ally read the EWT bit as long as it is set. When the 8192
clock cycle period is complete, the last read of the EWT
bit will successfully clear the bit and exit the routine.
Alternatively, software can poll the WTR bit until it is set,
then reset the watchdog via the RWT bit to clear the
8192 cycle count. The next read of the PCON register
will clear WTR bit as expected.
The Watchdog Timer is also reset whenever any other
type of reset is issued to the CPU and will begin its count
as soon as the reset condition is released and the ap-
plication software begins execution.
If operation without the Watchdog Timer is desired, then
the EWT bit should be cleared following any type of
reset by using the Timed Access register. This will
insure that the Watchdog Timer will never cause an
undesired reset during execution of the application soft-
ware.
WATCHDOG TIMER Figure 8–2
12 CLOCK
MACHINE CYCLE
COUNTER
122,800 CYCLE COUNTER
RWT
WTR
EWT