Mitsubishi Motors DS5000TK - Manual (Page 90)

USER’S GUIDE
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External Interrupts
The two external interrupts are INT0 and INT1. They
correspond to P3.2 and P3.3 respectively. These pins
become interrupts when the respective interrupt is
enabled. Otherwise, they are simply port pins. No other
special action is required. Each pin is sampled once per
machine cycle when the interrupts are enabled. INT0 is
enabled by setting the EX0 bit to a logic 1. INT1 is
enabled by setting the EX1 bit to a logic 1. These bits are
located at IE.0 and IE.2 respectively. The external inter-
rupts each have a status flag that indicates that the
condition has occurred. The flags are IE0 at TCON.1
and IE1 at TCON.3. These flags are set to a logic 1
when the interrupt condition occurs. They are cleared
when the CPU calls to the appropriate interrupt vector.
The external interrupts can be programmed to respond
to falling–edge or low–level activation. IT0 (TCON.0)
and IT1 (TCON.2) control the edge/level nature of INT0
and INT1 respectively. When ITn is a logic 0, the
associated interrupt is low–level activated. This causes
the IEn flag to be set for as long as the INTn pin remains
a logic 0. The interrupt (if enabled) will remain active dur-
ing this period. Note that the level interrupt is not
latched. Thus the pin must be held in a low state until the
ISR can be activated. If the INTn pin is brought to a logic
high prior to beginning the ISR, there will be no interrupt.
If the INTn is left at a logic low after the RETI instruction
of the ISR, another interrupt will be activated after one
instruction is executed.
Setting the ITn bit to a logic 1 causes the external inter-
rupt to be edge activated. This causes the device to
detect a falling edge on the INTn pin. This edge condi-
tion is latched until the interrupt is serviced. Thus in
edge mode, the INTn pin can go from a logic 1 to a logic
0, then back to a logic 1 and the interrupt will still be
active. After the falling–edge has been detected, the
INTn pin is subsequently ignored until after the ISR is
compete. The edge detector is actually a “pseudo–
edge” detector. Since the pin is actually sampled, the
condition must be a logic high for at least one machine
cycle and logic low for at least one machine cycle in
order to guarantee recognition of the falling edge. The
IEn flag is automatically cleared when the interrupt is
serviced.
Timer Interrupts
The Secure Microcontroller, like the 8051, has two inter-
nal timers. These timers can each generate an interrupt
when the value in the timer registers overflows. When
the Timer 0 overflows, the TF0 flag is set to al logic 1.
Likewise for the TF1 flag with respect to Timer 1. TF0 is
located at TCON.5 and TF1 is located at TCON.7.
These flags indicate the overflow condition. If the corre-
sponding timer interrupt is desired, then ET0 at IE.1 and
ET1 at IE.3 must be set to a logic 1 respectively. When
set, the timer overflow will cause an interrupt to the
appropriate vector location. If the interrupt is active, the
flag will automatically be cleared by the CPU.
Serial Port Interrupts
The on–chip serial port generates an interrupt when
either a word is received or a word is transmitted. The
interrupt is effectively a logical OR of the two conditions.
Each condition has its own flag. The flags operate
regardless of whether the interrupt has been enabled.
RI is located at SCON.0 and represents a serial word
received. TI is located at SCON.1 and represents a
serial word transmitted. Each flag is set to a logic 1 to
indicate an active state. Since there are two flags for one
interrupt, these flags are used by the ISR to determine
the cause of the interrupt. The flags must be cleared by
software to clear the interrupt condition. The serial inter-
rupt is activated by setting the ES bit at IE.4 to a logic 1.
Power–fail Warning Interrupt
The Secure Microcontroller family adds a new interrupt
to the standard 8051 collection. It is used in conjunction
with the power monitor and nonvolatile memory. During
a power down or brown out, as V
CC
is falling, the Secure
Microcontroller can generate an early warning Power–
fail Interrupt (PFW). This allows the software to save
critical data prior to entering a reset condition. Since the
nonvolatile RAM is not affected by a reset, this data is
effectively saved. Software can use the PFW to save the
current routine, current data, shut off external functions,
or simply to enter a known region of memory for the
power down.
The PFW is enabled by setting the EPFW bit at PCON.3
to a logic 1. The Power–fail Warning flag (PFW) is
located at PCON.5. When ever V
CC
drops below the
V
PFW
voltage threshold, the PFW flag will be set to a
logic 1. This flag will be cleared when read by software.
If the voltage is still below the V
PFW
, the flag will again
be set immediately. This will occur regardless of
whether the interrupt is enabled. The V
PFW
voltage is
different for each member of the Secure Microcontroller
family. Check the electrical specifications for details.
Note that the PFW interrupt is not controlled by the EA