Texas Instruments TMS320C2XX - Manual (Page 119)

Interrupts
5-20
Figure 5–6 summarizes how maskable interrupts are handled by the CPU.
Figure 5–6. Maskable Interrupt Operation Flow Chart
Interrupt request sent to CPU
Corresponding IFR flag bit set
Interrupts enabled
(INTM bit = 0)
?
Interrupt
unmasked?
Interrupt acknowledged
Yes
Yes
No
No
INTM bit set to 1
PC saved on stack
Interrupt service routine run
Return instruction restores PC
Program continues
5.6.4 Interrupt Flag Register (IFR)
The 16-bit interrupt flag register (IFR), located at address 0006h in data
memory space, contains flag bits for all the maskable interrupts. When a mask-
able interrupt request reaches the CPU, the corresponding flag is set to 1 in
the IFR. This indicates that the interrupt is pending, or waiting for acknowl-
edgement.
Read the IFR to identify pending interrupts, and write to the IFR to clear pend-
ing interrupts. To clear an interrupt request (and set its IFR flag to 0), write a