Texas Instruments TMS320C2XX - Manual (Page 226)

Load Accumulator With Shift LACC
7-73 Assembly Language Instructions
Execution Increment PC, then ...
Event
Addressing mode
(data-memory address)
×
2 shift →
ACC Direct or indirect
(data-memory address)
×
2 16 →
ACC Direct or indirect (shift of 16)
lk
×
2 shift →
ACC Long immediate
Status Bits Affected by
SXM
Description The contents of the specified data-memory address or a 16-bit constant are
left shifted and loaded into the accumulator. During shifting, low-order bits are
zero filled. High-order bits are sign extended if SXM = 1 and zeroed if SXM = 0.
Words Words Addressing mode
1 Direct or indirect
2 Long immediate
Cycles for a Single LACC Instruction (Using Direct and Indirect Addressing)
Program
Operand ROM DARAM SARAM External
DARAM 1 1 1 1+p
SARAM 1 1 1, 2 † 1+p
External 1+d 1+d 1+d 2+d+p
† If the operand and the code are in the same SARAM block
Cycles for a Repeat (RPT) Execution of an LACC Instruction (Using Direct
and Indirect Addressing)
Program
Operand ROM DARAM SARAM External
DARAM n n n n+p
SARAM n n n, n+1 † n+p
External n+nd n+nd n+nd n+1+p+nd
† If the operand and the code are in the same SARAM block
Cycles for a Single LACC Instruction (Using Immediate Addressing)
ROM DARAM SARAM External
2 2 2 2+2p
Cycles