Texas Instruments TMS320C2XX - Manual (Page 542)

F-5 Glossary
clock mode (clock generator): One of the modes which sets the internal
CPU clock frequency to a fraction or multiple of the frequency of the input
clock signal CLKIN. The ’C209 has two clock modes (
÷
2 and
×
2); other
’C2xx devices have four clock modes (
ч
2,
Ч
1,
Ч
2, and
×
4).
clock mode (synchronous serial port): See clock mode bit (MCM).
clock mode bit (MCM): Bit 2 of the synchronous serial port control register
(SSPCR); determines whether the source signal for clocking synchro-
nous serial port transfers is external or internal.
CNF bit: DARAM configuration bit. Bit 12 in status register ST1. CNF is used
to determine whether the on-chip RAM block B0 is mapped to program
space or data space.
codec: A device that codes in one direction of transmission and decodes in
another direction of transmission.
COFF: Common object file format. An output format that promotes modular
programming by supporting sections; the format of files created by the
TMS320C1x/C2x/C2xx/C5x assembler and linker.
context saving/restoring: Saving the system status when the device en-
ters a subroutine (such as an interrupt service routine) and restoring the
system status when exiting the subroutine. On the ’C2xx, only the pro-
gram counter value is saved and restored automatically; other context
saving and restoring must be performed by the subroutine.
continuous mode: A synchronous serial port mode in which only one frame
synchronization pulse is necessary to transmit or receive several con-
secutive packets at maximum frequency. See also
burst mode.
CPU: Central processing unit. The ’C2xx CPU is the portion of the processor
involved in arithmetic, shifting, and Boolean logic operations, as well as
the generation of data- and program-memory addresses. The CPU in-
cludes the central arithmetic logic unit (CALU), the multiplier, and the
auxiliary register arithmetic unit (ARAU).
CPU cycle: The time required for the CPU to go through one logic phase
(during which internal values are changed) and one latch phase (during
which the values are held constant).
current AR: See current auxiliary register.
current auxiliary register: The auxiliary register pointed to by the auxiliary
register pointer (ARP). The auxiliary registers are AR0 (ARP = 0)
through AR7 (ARP = 7). See also
auxiliary register; next auxiliary regis-
ter.
Glossary