Texas Instruments TMS320C2XX - Manual (Page 121)

Interrupts
5-22
Bit 3 RINT — Receive interrupt flag. Bit 3 is tied to the receive interrupt for the synchro-
nous serial port.
To avoid double interrupts, write a 1 to this bit in the interrupt service
routine.
RINT = 0 Interrupt RINT is not pending.
RINT = 1 Interrupt RINT is pending.
Bit 2 TINT — Timer interrupt flag. Bit 2 is tied to the timer interrupt, TINT.
TINT = 0 Interrupt TINT is not pending.
TINT = 1 Interrupt TINT is pending.
Bit 1 INT2/INT3 — Interrupt 2/Interrupt 3 flag. The INT2 pin and the INT3 pin are both
tied to bit 1. If INT2 is requested, INT2/INT3 and FINT2 (of the ICR) are both automati-
cally set to 1. If INT3 is requested, INT2/INT3 and FINT3 (of the ICR) are both auto-
matically set to 1.
INT2/INT3 = 0 Neither INT2 nor INT3 is pending.
INT2/INT3 = 1 At least one of the two interrupts is pending. To determine which
one is pending or if both are pending, read flag bits FINT2 and
FINT3 in the interrupt control register (ICR). FINT2 and FINT3 are
not automatically cleared when INT2 and INT3 are acknowledged
by the CPU; they must be cleared by the interrupt service routine.
Bit 0 HOLD/INT1 — HOLD/Interrupt 1 flag. Bit 0 is a flag for HOLD or INT1. The operation
of the HOLD/INT1 pin differs depending on the value of the MODE bit in the interrupt
control register (ICR). When MODE = 1, an interrupt is triggered only by a negative
edge on the pin. When MODE = 0, interrupts can be triggered by both a negative edge
and a positive edge. This is necessary to implement the ’C2xx HOLD operation (see
Section 4.7,
Direct Memory Access Using The HOLD Operation, on page 4-27).
HOLD/INT1 = 0 HOLD/INT1 is not pending.
HOLD/INT1 = 1 HOLD/INT1 is pending.
5.6.5 Interrupt Mask Register (IMR)
The 16-bit interrupt mask register (IMR), located at address 0004h in data-
memory space, is used for masking external and internal hardware interrupts.
Neither NMI nor RS is included in the IMR; thus, IMR has no effect on these
interrupts.
Read the IMR to identify masked or unmasked interrupts, and write to the IMR
to mask or unmask interrupts. To unmask an interrupt, set its corresponding
IMR bit to 1. To mask an interrupt, set its corresponding IMR bit to 0. At reset,
the IMR bits are all set to 0, masking all the maskable interrupts.