Texas Instruments TMS320C2XX - Manual (Page 221)

IDLE Idle Until Interrupt
7-68
Syntax IDLE
Operands None
Opcode 0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
0 1 0 0 0 1 0 0 0 1 1 1 1 1 0 1
Execution Increment PC, then wait for unmasked or nonmaskable hardware interrupt.
Status Bits Affected by
INTM
Description The IDLE instruction forces the program being executed to halt until the CPU
receives a request from an unmasked hardware interrupt (external or internal),
NMI, or reset. Execution of the IDLE instruction causes the ’C2xx to enter a
power-down mode. The PC is incremented once before the ’C2xx enters pow-
er down; it is not incremented during the idle state. On-chip peripherals remain
active; thus, their interrupts are among those that can wake the processor.
The idle state is exited by an unmasked interrupt even if INTM is 1. (INTM, the
interrupt mode bit of status register ST0, normally disables maskable inter-
rupts when it is set to 1.) When the idle state is exited by an unmasked inter-
rupt, the CPU’s next action, however, depends on INTM:
- If INTM is 0, the program branches to the corresponding interrupt service
routine.
- If INTM is 1, the program continues executing at the instruction following
the IDLE.
NMI and reset are not maskable; therefore, if the idle state is exited by NMI or
reset, the corresponding interrupt service routine will be executed, regardless
of INTM.
Words 1
Cycles for a Single IDLE Instruction
ROM DARAM SARAM External
1 1 1 1+p
Example IDLE ;The processor idles until a hardware reset,
;a hardware NMI, or an unmasked interrupt
;occurs.
Cycles