Texas Instruments TMS320C2XX - Manual (Page 70)

Local Data Memory
4-8
4.3.1 Data Page 0 Address Map
Table 4–2 shows the address map of data page 0 (addresses 0000h–007Fh).
Note the following:
- Three memory-mapped registers can be accessed with zero wait states:
J Interrupt mask register (IMR)
J Global memory allocation register (GREG)
J Interrupt flag register (IFR)
- The test/emulation reserved area is used by the test and emulation sys-
tems for special information transfers.
Do Not Write to Test/Emulation Addresses
Writing to the test/emulation addresses can cause the device to
change its operational mode and, therefore, affect the operation of
an application.
- The scratch-pad RAM block (B2) includes 32 words of DARAM that pro-
vide for variable storage without fragmenting the larger RAM blocks,
whether internal or external. This RAM block supports dual-access opera-
tions and can be addressed with any data-memory addressing mode.
Table 4–2. Data Page 0 Address Map
Address Name Description
0000h–0003h – Reserved
0004h IMR Interrupt mask register
0005h GREG Global memory allocation register
0006h IFR Interrupt flag register
0023h–0027h – Reserved
002Bh–002Fh – Reserved for test/emulation
0060h–007Fh B2 Scratch-pad RAM (DARAM B2)