Texas Instruments TMS320C2XX User Manual

Page 581

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Index

Index-18

program memory

(continued)

configuration

RAM (dual-access)

’C203

4-33

’C204

4-36

’C209

11-8

RAM (single-access)

11-7

ROM

’C204

4-36

’C209

11-7

description

4-5

external interfacing

4-5

caution about proper timing

4-5

program memory select pin (PS)

definition

4-3

shown in figure

4-6

program read bus (PRDB)

2-3

program-address generation (diagram)

5-2

protocol, bus, in emulator system

E-4

PS (program memory select pin)

definition

4-3

shown in figure

4-6

PSC (timer prescaler counter)

’C203/C204

8-11

’C209

11-15

definition

F-18

PSHD instruction

7-139

PSLWS bits

8-15

PSUWS bits

8-15

PSWS bit

11-17

PUSH instruction

7-141

push operation (diagram)

5-5

R

R/W (read/write pin)

4-4

RAM (on-chip)

dual-access

configuration

’C203

4-33

’C204

4-36

’C209

11-8

description

2-7

single-access

configuration

11-7

description

2-8

RAMEN (single-access RAM enable pin)

definition

4-4

use in configuring memory

11-7

RD (read select pin)

definition

4-4

shown in figure

4-6, 4-10, 4-13, 4-15

read select pin (RD)

definition

4-4

shown in figure

4-6, 4-10, 4-13, 4-15

read/write pin (R/W)

4-4

READY (external device ready pin)

definition

4-4

generating wait states with

8-14

receive interrupt

asynchronous serial port

10-17

enabling/disabling (RIM bit)

10-8

synchronous serial port

9-6

receive pin

asynchronous serial port (RX)

10-4

detecting break on (BI bit)

10-10

synchronous serial port (DR)

9-4

receive register

asynchronous serial port (ADTR)

10-4

detecting overrun in (OE bit)

10-11

detecting when empty (DR bit)

10-11

synchronous serial port (SDTR)

9-5

receive shift register

asynchronous serial port (ARSR)

10-5

synchronous serial port (RSR)

9-5

register summary

A-1 to A-14

registers

addresses and reset values

A-2

asynchronous serial port

baud-rate divisor register (BRD)

10-13

control register (ASPCR)

10-7

I/O status register (IOSR)

10-10

receive shift register (ARSR)

10-5

transmit shift register (AXSR)

10-5

auxiliary registers, current auxiliary regis-

ter

6-13

auxiliary registers (AR0–AR7)

current auxiliary register

6-9

next auxiliary register

6-11

baud-rate divisor register (BRD)

10-13

CLKOUT1-pin control (CLK) register

8-7

I/O status register (IOSR)

10-10

interrupt control register (ICR)

5-24 to 5-38

interrupt flag register (IFR)

5-20 to 5-22

’C209

11-12 to 11-18

interrupt mask register (IMR)

5-22 to 5-24

’C209

11-13 to 11-18

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