Texas Instruments TMS320C2XX - Manual (Page 31)

Key Features of the TMS320C2xx
1-6
1.3 Key Features of the TMS320C2xx
Key features on the various ’C2xx devices are:
- Speed:
J 50-, 35-, or 25-ns execution time of a single-cycle instruction
J 20, 28.5, or 40 MIPS
- Code compatibility with other TMS320 fixed-point devices:
J Source-code compatible with all ’C1x and ’C2x devices
J Upward compatible with the ’C5x devices
- Memory:
J 224K words of addressable memory space (64K words of program
space, 64K words of data space, 64K words of I/O space, and 32K
words of global space)
J 544 words of dual-access on-chip RAM (288 words for data and 256
words for program/data)
J 4K words on-chip ROM or 32K words on-chip flash memory (on
selected devices)
J 4K words of single-access on-chip RAM (on selected devices)
- CPU:
J 32-bit arithmetic logic unit (CALU)
J 32-bit accumulator
J 16-bit
×
16-bit parallel multiplier with 32-bit product capability
J Three scaling shifters
J Eight 16-bit auxiliary registers with a dedicated arithmetic unit for indi-
rect addressing of data memory
- Program control:
J 4-level pipeline operation
J 8-level hardware stack
J User-maskable interrupt lines