Texas Instruments TMS320C2XX - Manual (Page 71)

Local Data Memory
4-9 Memory and I/O Spaces
4.3.2 Interfacing With External Local Data Memory
While the ’C2xx is accessing the on-chip local data-memory blocks, the exter-
nal memory signals DS and STRB are in high impedance. The external buses
are active only when the ’C2xx is accessing locations within the address
ranges mapped to external memory. An active DS signal indicates that the ex-
ternal buses are being used for data memory. Whenever the external buses
are active (when external memory or I/O space is being accessed) the ’C2xx
drives the STRB signal low.
For fast memory interfacing, it is important to select external memory with fast
access time. If fast memory is not available, or if speed is not a serious consid-
eration, you can use the the READY signal and/or the on-chip wait-state gen-
erator to create wait states.
Figure 4–3 shows an example of interfacing to external data memory. In the
figure 8K
×
16-bit static memory is interfaced to the ’C2xx using two 8K
×
8-bit
RAMs. The RAM devices must have fast access times if the internal instruction
speed is to be maintained.
Obtain the Proper Timing Information
When interfacing memory with high-speed ’C2xx devices, refer to
the data sheet for that ’C2xx device for the required access, delay,
and hold times.