Texas Instruments TMS320C2XX User Manual
Page 150
Indirect Addressing Mode
6-14
Table 6–3. Field Bits and Notation for Indirect Addressing
Instruction Opcode Bits
15
–
8 7 6 5 4 3 2 1 0
Operand(s)
Operation
←
8 MSBs
→
1
0
0
0
0
←
NAR
→
*
No manipulation of current AR
←
8 MSBs
→
1
0
0
0
1
←
NAR
→
*,AR
n
NAR
→
ARP
←
8 MSBs
→
1
0
0
1
0
←
NAR
→
*–
current AR – 1
→
current AR
←
8 MSBs
→
1
0
0
1
1
←
NAR
→
*–,AR
n
current AR – 1
→
current AR
NAR
→
ARP
←
8 MSBs
→
1
0
1
0
0
←
NAR
→
*+
current AR + 1
→
current AR
←
8 MSBs
→
1
0
1
0
1
←
NAR
→
*+,AR
n
current AR + 1
→
current AR
NAR
→
ARP
←
8 MSBs
→
1
1
0
0
0
←
NAR
→
*BR0–
current AR –
rcAR0
→
current AR †
←
8 MSBs
→
1
1
0
0
1
←
NAR
→
*BR0–,AR
n
current AR –
rcAR0
→
current AR
NAR
→
ARP †
←
8 MSBs
→
1
1
0
1
0
←
NAR
→
*0–
current AR – AR0
→
current AR
←
8 MSBs
→
1
1
0
1
1
←
NAR
→
*0–,AR
n
current AR – AR0
→
current AR
NAR
→
ARP
←
8 MSBs
→
1
1
1
0
0
←
NAR
→
*0+
current AR + AR0
→
current AR
←
8 MSBs
→
1
1
1
0
1
←
NAR
→
*0+,AR
n
current AR + AR0
→
current AR
NAR
→
ARP
←
8 MSBs
→
1
1
1
1
0
←
NAR
→
*BR0+
current AR +
rcAR0
→
current AR †
←
8 MSBs
→
1
1
1
1
1
←
NAR
→
*BR0+,AR
n
current AR +
rcAR0
→
current AR
NAR
→
ARP †
† Bit-reversed addressing mode
Legend:
rc
Reverse carry propagation
NAR
Next AR
n
0, 1, 2, ..., or 7
8 MSBs
Eight bits determined by instruction type and (sometimes) shift information
→
Is loaded into