Texas Instruments TMS320C2XX User Manual
Page 549
F-12
INT1–INT3:
Three external pins used to generate general-purpose hard-
ware interrupts.
internal interrupt:
A hardware interrupt caused by an on-chip peripheral.
interrupt:
A signal sent to the CPU that (when not masked or disabled)
forces the CPU into a subroutine called an interrupt service routine (ISR).
This signal can be triggered by an external device, an on-chip peripheral,
or an instruction (INTR, NMI, or TRAP).
interrupt acknowledge signal (IACK):
An output signal on the ’C209 that
indicates that an interrupt has been received and that the program count-
er is fetching the interrupt vector that will force the processor into the ap-
propriate interrupt service routine.
interrupt control register (ICR):
A 16-bit register used to differentiate
HOLD and INT1 and to individually mask and flag INT2 and INT3.
interrupt flag register (IFR):
A 16-bit memory-mapped register that indi-
cates pending interrupts. Read the IFR to identify pending interrupts and
write to the IFR to clear selected interrupts. Writing a 1 to any IFR flag
bit clears that bit to 0.
interrupt latency:
The delay between the time an interrupt request is made
and the time it is serviced.
interrupt mask register (IMR):
A 16-bit memory-mapped register used to
mask external and internal interrupts. Writing a 1 to any IMR bit position
enables the corresponding interrupt (when INTM = 0).
interrupt mode bit (INTM):
Bit 9 in status register ST0; either enables all
maskable interrupts that are not masked by the IMR or disables all mask-
able interrupts.
interrupt service routine (ISR):
A module of code that is executed in re-
sponse to a hardware or software interrupt.
interrupt trap:
See
interrupt service routine (ISR).
interrupt vector:
A branch instruction that leads the CPU to an interrupt ser-
vice routine (ISR).
interrupt vector location:
An address in program memory where an inter-
rupt vector resides. When an interrupt is acknowledged, the CPU
branches to the interrupt vector location and fetches the interrupt vector.
INTM bit:
See
interrupt mode bit (INTM).
Glossary