Texas Instruments TMS320C2XX - Manual (Page 130)

Interrupts
5-31 Program Control
For an external, maskable hardware interrupt, a minimum latency of eight
cycles is required to synchronize the interrupt externally, recognize the inter-
rupt, and branch to the interrupt vector location. On the ninth cycle, the inter-
rupt vector is fetched. For a software interrupt, the minimum latency consists
of four cycles needed to branch to the interrupt vector location.
Latency for pipeline protection
Multicycle instructions add additional cycles to empty the pipeline. Instructions
may become multicycle for these reasons:
- An instruction that writes to or reads from external memory may be
delayed by wait states generated by the external READY pin or the on-
chip wait-state generator. These wait states may affect the instruction be-
ing executed at the time the interrupt is requested, and they may affect the
interrupt itself if the interrupt vector must be fetched from external memory.
- If an interrupt occurs during a HOLD operation and the interrupt vector
must be fetched from external memory, the vector cannot be fetched until
HOLDA is deasserted.
- When repeated with RPT, instructions run parallel operations in the pipe-
line and the context of these additional parallel operations cannot be
saved in an interrupt service routine. To protect the context of the repeated
instruction, the CPU locks out all interrupts except reset until the RPT loop
completes.
Note:
Reset (RS) is not delayed by multicycle instructions. NMI can be delayed by
multicycle instructions.
Latency for stack overflow protection
A return address (incremented program counter value) is forced onto the hard-
ware stack every time the CPU follows another interrupt service routine or oth-
er subroutine. However, the ’C2xx has a feature that can help you to keep the
hardware stack from overflowing. Interrupts cannot be processed between the
CLRC INTM (enable maskable interrupts) instruction and the next instruction
in a program sequence. This ensures that a return instruction that directly fol-
lows CLRC INTM will be executed before an interrupt is processed. The return
instruction will pop the previous return address off the top of the stack before
the new return address is pushed onto the stack. If the interrupt were to occur