Texas Instruments TMS320C2XX - Manual (Page 171)

How To Use the Instruction Descriptions
7-18
The instruction-cycle timings are based on the following assumptions:
- At least the next four instructions are fetched from the same memory sec-
tion (internal or external) that was used to fetch the current instruction (ex-
cept in the case of PC discontinuity instructions, such as B, CALL, etc.)
- In the single-execution mode, there is no pipeline conflict between the cur-
rent instruction and the instructions immediately preceding or following
that instruction. The only exception is the conflict between the fetch phase
of the pipeline and the memory read/write (if any) access of the instruction
under consideration. See Section 5.2,
Pipeline, on page 5-7 for more in-
formation about pipeline operation.
- In the repeat execution mode, all conflicts caused by the pipelined execu-
tion of an instruction are considered.
7.2.9 Examples
Example code is included for each instruction. The effect of the code on
memory and/or registers is summarized. Program code is shown in a
special typeface . The sample code is then followed by a verbal or graph-
ic description of the effect of that code. Consider this example of the ADD
instruction:
ADD *+,0,AR0
Before Instruction After Instruction
ARP 4 ARP 0
AR4 0302h AR4 0303h
Data Memory Data Memory
302h 2h 302h 2h
ACC X 2h ACC 0 04h
C C
Here are the facts and events represented in this example:
- The auxiliary register pointer (ARP) points to the current auxiliary register.
Because ARP = 4, the current auxiliary register is AR4.
- When the addition takes place, the CPU follows AR4 to data-memory
address 0302h. The content of that address, 2h, is added to the content
of the accumulator, also 2h. The result (4h) is placed in the accumulator.
(Because the second operand of the instruction specifies a left shift of 0,
the data-memory value is not shifted before being added to the accumula-
tor value.)
- The instruction specifies an increment of one for the contents of the cur-
rent auxiliary register (*+); therefore, after the addition is performed, the
content of AR4 is incremented to 0303h.