Texas Instruments TMS320C2XX User Manual
Page 573
Index
Index-10
IMR (interrupt mask register)
bits
’C203/C204
’C209
11-13
in interrupt acknowledgement process
quick reference
IN instruction
IN0 bit
indirect addressing
description
effects on auxiliary register pointer
(ARP)
effects on current auxiliary register
examples
modifying auxiliary register content
opcode format
operands
operation types
options
possible opcodes
input clock modes
’C203/C204
’C209
input scaling section of CPU
input shifter
input/output space.
See I/O space
input/output status register (IOSR)
description
detecting change on pins IO0–IO3
reading current logic level on pins
IO0–IO3
instruction register (IR), definition
instruction set, key features
instructions
Boolean logic
AND
CMPL (complement/NOT)
OR
XOR (exclusive OR)
compared with those of other TMS320 de-
vices
conditional
branch (BCND)
call (CC)
7-60
conditions that may be tested
return (RETC)
stabilization of conditions
using multiple conditions
instructions
(continued)
CPU halt until hardware interrupt (IDLE)
delay/no operation (NOP)
descriptions
how to use
enhanced
idle until hardware interrupt (IDLE)
interrupt
branch to NMI interrupt vector location
(NMI)
branch to specified interrupt vector location
(INTR)
branch to TRAP interrupt vector location
(TRAP)
negate accumulator (NEG)
no operation (NOP)
normalize (NORM)
OR
power down until hardware interrupt
(IDLE)
repeat next instruction n times
description (RPT)
introduction
stack
pop top of stack to data memory
(POPD)
pop top of stack to low accumulator bits
(POP)
push data memory value onto stack
(PSHD)
push low accumulator bits onto stack
(PUSH)
status registers ST0 and ST1
clear control bit (CLRC)
load (LST)
load data page pointer (LDP)
modify auxiliary register pointer (MAR)
7-111
set control bit (SETC)
set product shift mode (SPM)
store (SST)
summary
test bit specified by TREG (BITT)
test specified bit (BIT)
INT1 bit (’C209)
in interrupt flag register (IFR)
in interrupt mask register (IMR)