Achronix Speedster22i PCIe - Manual (Page 13)

UG030, April 26, 2013 13
synchronization techniques can be used to enable support for a wide variety
of AXI clock rates.
User’s Task: It is important to consume target write and read transactions
relatively quickly as it is possible to stall PCI Express completions (used for
S2C DMA for example) if target write and read transactions are allowed to
languish in the PCI Express Core Receive Buffer.
Target Only Design
The Target-Only design is the simplest design to implement and works well
if the master device transmits packets with larger burst widths. Throughput
in PCI Express (and in its predecessors PCI and PCI-X) is directly
proportional to burst size, so small transaction burst sizes result in low
throughput.
User’s Task: To fix the inherent limitations of CPU and other small burst
size masters, a design must be able to master the PCI Express bus and enact
transactions with larger burst sizes (see the
AXI Master Interface section for
additional details).
Still, the Target-Only design is ideal, due to its simplicity and hence smaller
design size, for lower bandwidth applications and applications where
another master is available to master transactions at larger burst sizes.
System software is also easier to write for target-only applications since only
basic CPU move instructions need to be used and the software complexities
of a DMA-based system (interrupts, DMA system memory allocation, etc.)
do not need to be handled.
AXI Back-End DMA Interface
The AXI DMA Interface is the mechanism through which user logic interacts
with the DMA Engine. The AXI DMA Interface orchestrates the flow of DMA
data between user logic and PCI Express.
The AXI DMA System to Card and AXI DMA Card to System interfaces
support multiple AXI protocol options (which are selected with the DMA
Back End DMA Engine inputs c2s/s2c_fifo_addr_n):

AXI3/AXI4

AXI4-Stream
Addressable FIFO DMA
When a DMA Engine is configured to implement an AXI3/AXI4 interface,
system software can set the “Addressable FIFO DMA” Descriptor bit in all
Descriptors of an application DMA transfer to instruct the DMA Back End to
provide the same starting AXI address provided by software for all AXI