Achronix Speedster22i PCIe - Manual (Page 24)

UG030, April 26, 2013 24
Port List
SerDes Interface
Table 2: SerDes Interface Pin Descriptions
Pin Name Direction Clock Description
pcie_refclk_p[7:0] Input Reference Clock Input
pcie_refclk_n[7:0] Input Reference Clock Input
tx_p[7:0] Output Serial Transmit
tx_n[7:0] Output Serial Transmit
rx_p[7:0] Input Serial Receive
rx_n[7:0] Input Serial Receive
i_serdes_sbus_req [7:0] Input i_sbus_clk SerDes side SBUS request
i_serdes_sbus_data [15:0] Input i_sbus_clk SerDes side SBUS data to write
o_serdes_sbus_data [15:0] Output i_sbus_clk SerDes side SBUS data to read
o_serdes_sbus_ack [7:0] Output i_sbus_clk SerDes side SBUS
acknowledgement