Achronix Speedster22i PCIe - Manual (Page 25)

UG030, April 26, 2013 25
Fabric-Side Interface
Table 3: Fabric-Side Port Descriptions
Port Name Direction Clock Description
perst_n Input user_clk Fundamental Reset; active-low asynchronous
assert, synchronous de-assert; resets the entire
core except for Configuration Registers which
are defined by PCI Express to be unaffected by
fundamental reset; on rst_n de-assertion the
core starts in the Detect Quiet Link Training
and Status State Machine (LTSSM) state with
the Physical Layer down (mgmt_pl_link_up_o
== 0) and Data Link Layer down
(mgmt_dl_link_up_o == 0).
clk_out Output core_clk Core clock; all core ports are synchronous to
the rising edge of clk_out.
The PIPE Specification defines two possible
approaches to adapting to changes in the line
rate of PCI Express (changing between 2.5, 5,
and 8GT/s operation). The core natively
supports PHY that implement the PIPE
constant-data-width, variable-clock-frequency
PIPE interface and PHY that implement the
PIPE variable-data-width, constant-clock-
frequency PIPE interface.
The frequency of clk_out must be the full-
bandwidth frequency for the PHY per-lane
data width (Core Data Width/Max Lane
Width; which is static for a given core
configuration) and the current line rate:
16-bit Per-Lane Data Width core
configurations:

8.0 GT/s -> 500 MHz

5.0 GT/s -> 250 MHz

2.5 GT/s -> 125 MHz
clk_out is connected to the PHY’s clk_out, or a
binary multiple/divisor of clk_out when PHY
and Core have different data widths.
Note: Per PCI Express Specification, PHYs
must use the same clock reference as the
remote PCIe device to be compatible with
systems implementing Spread Spectrum