Achronix Speedster22i PCIe - Manual (Page 31)

UG030, April 26, 2013 31
Port Name Direction Clock Description
targets Base Address
Region 1
 Bit[0] – (1) if the TLP
targets Base Address
Region 0
vc0_rx_cmd_data is valid for the entire packet
(from vc0_rx_sop == 1 through vc0_rx_eop ==
vc0_rx_en == 1)
bypass_interrupt
Input bypass_clk mgmt_interrupt is used to generate interrupt
events on the PCI Express link.
Interrupt support is enabled by setting
mgmt_cfg_constants[128] (Interrupt Enable) ==
1.
The core contains the following two interrupt
configuration options:
 Single Interrupt Configuration
o Support for 1 Legacy Interrupt
o Support for 1 MSI Interrupt
o mgmt_interrupt is used to
signal both Legacy and MSI
interrupts
 Multiple Interrupt Configuration
o Support for 1 Legacy Interrupt
o Support for up to 32 MSI
Interrupts
o Support for up to 2048 MSI-X
Interrupts
o mgmt_interrupt is used to
signal only Legacy interrupts
o mgmt_interrupt_msix_req,
mgmt_interrupt_msix_ack and
mgmt_interrupt_msix_vector,
available only in this
configuration, are used to
signal MSI and MSI-X
interrupts.
System software selects MSI-X, MSI, or Legacy
Interrupt mode as part of the boot process by
writing MSI-X_Enable==1 or MSI_Enable ==1
or leaving both MSI-X_Enable and MSI_Enable
Configuration Registers at their default
disabled value.
The current interrupt mode of operation is
available by monitoring
mgmt_cfg_status[1296] (MSI_Enable) and