Achronix Speedster22i PCIe - Manual (Page 20)

UG030, April 26, 2013 20
• Control - During packet to Descriptor mapping, software
writes the number of bytes that it wrote into the Descriptor
into S2CDescByteCount. If EOP=0, then S2CDescByteCount
must be the same as the Descriptor size DescByteCount. If
EOP=1 and the packet ends before filling the entire
Descriptor, then S2CDescByteCount is less than the
Descriptor size DescByteCount. The transmitted packet size
is the sum of the S2CDescByteCount fields for all
Descriptors that are part of a packet
• Status – After completing a DMA operation, the DMA
Engine writes the number of bytes transferred for the
Descriptor into S2CDescByteCount. Except for error
conditions, S2CDescByteCount should be the same as
originally provided.
• Note: S2CDescByteCount is 20-bits so supports Descriptors
up to 2^20-1 bytes. Note that since packets can span multiple
Descriptors, packets may be significantly larger than the
Descriptor size limit.
AXI Master Interface
The AXI Master Interface is an AXI4-Lite Slave interface that enables the user
to:

Generate PCI Express requests with up to 1 DWORD (32-bit)
payload

Write and read DMA Back-End internal registers to start DMA
operation and obtain interrupt status
The AXI Master Interface implements a register set to enable the
above functions.

A PCI Express request is carried out by writing the PCI Express-
specific information (PCI Express Address, Format and Type, etc.) to
the register set and then writing to another register to execute the
request.

DMA Registers are made accessible via AXI reads and writes
The design in
Figure 7 contains the same elements as the Target-Only
design described in section AXI Target Interface, but is enhanced with Direct
Memory Access (DMA) capability to achieve greater throughput. For the
transfer of large volumes of data, the DMA has inherently better throughput
than target-only designs both because the burst sizes are generally much
larger, but also because DMA read transactions can be cascaded while most
software using CPU move instructions will block on a read until it