Achronix Speedster22i PCIe - Manual (Page 29)

UG030, April 26, 2013 29
Port Name Direction Clock Description
vc0_rx_sop is asserted, the user may assert
vc0_rx_en as desired to consume the TLP.
bypass_rx_eop Output bypass_clk End of TLP indicator; set == 1 coincident with
the last vc0_rx_data word in each packet.
bypass_rx_ecrc_error Output bypass_clk ECRC error indicator; set == 1 from vc0_rx_sop
to vc0_rx_eop inclusive for received TLPs
which contain a detected ECRC error. Clear ==
0 otherwise.
vc0_rx_err_ecrc only reports ECRC errors
when ECRC checking is enabled. ECRC
checking is enabled by software through the
AER Capability.
Packets with ECRC errors are presented on the
Receive Interface in the same format that they
are received including the TLP Digest (ECRC).
User’s task: The user design must decide how
to handle/recover from the error including
whether to use the TLP with the error. ECRC
errors need for higher level software to
correct/handle the error since it is unknown
where in the PCIe hierarchy the error occurred
and PCIe does not have a standard mechanism
for rebroadcasting packets end to end as it
does for a given PCIe link via the Link CRC.
bypass_rx_decode_info[12:0] Output bypass_clk TLP type indicator; provides advance
information about the TLP to facilitate TLP
consumption; this port has a different meaning
in Root Port and Switch Modes.
The core decodes received TLP headers to
determine their destination; the core passes
this information to the Transaction Layer
Interface by asserting the appropriate bits in
this field. See the description of
mgmt_cfg_constants: Base Address Cfg[5:0]
sub fields in
Individual bits of vc0_rx_cmd_data[12:0] carry
the following meaning:

Bits[12:10] – Traffic Class of the packet

Bit[9] – Completion/Base Address
Region indicator
1: indicates the TLP is a Completion or
Message routed by ID
0: indicates the TLP is a read or write
request (or a Message routed by
address) targeting a Base Address
Region; the remaining bits in this field