Achronix Speedster22i PCIe - Manual (Page 34)

UG030, April 26, 2013 34
Port Name Direction Clock Description
set to 1 and mgmt_interrupt_msix_vector
indicates the interrupt vector that is to be
transmitted. Once mgmt_interrupt_msix_req is
set, mgmt_interrupt_msix_req and
mgmt_interrupt_msix_vector must remain at
their same values until
mgmt_interrupt_msix_ack is asserted == 1
indicating that the requested interrupt message
was transmitted.
If MSI_En == 1, then the design is operating in
MSI interrupt mode. The core supports up to
the maximum of 32 interrupt vectors
supported by the MSI Capability. The interrupt
vector number to transmit is placed on
mgmt_interrupt_msix_vector[4:0] and
mgmt_interrupt_msix_vector[127:5] is set to all
zeros. The core transmits MSI Interrupts by
transmitting a Memory Write containing the
address and data value (with lower data bits
modified to signal the vector number) setup by
software in the MSI Capability. System
software may not allocate as many MSI
interrupt vectors as requested by the design so
user hardware and software must be designed
to share interrupts if required. The core
performs the necessary aliasing (dropping the
higher mgmt_interrupt_msix_vector[4:0] bits
as required) so the user may drive a full 5-bit
vector number even if fewer vectors are
assigned.
If MSI-X_En == 1, then the design is operating
in MSI-X interrupt mode. The core supports up
to the maximum of 2048 interrupt vectors
supported by the MSI-X Capability.
User’s task: In MSI-X Interrupt mode, the user
implements the required MSI-X Table and
MSI-X PBA in memory space mapped by a
Base Address Register. Each Table entry/vector
consists of a 64-bit address, 32-bit data value,
and 32-bit vector control word. To request an
interrupt be transmitted, the MSI-X Table entry
corresponding to the desired vector number is
fetched and placed onto
mgmt_interrupt_msix_vector[127:0] and
mgmt_interrupt_msix_req is set == 1. If the
interrupt is masked by the MSI-X Capability