Achronix Speedster22i PCIe - Manual (Page 42)

UG030, April 26, 2013 42
Pin Name Direction Clock Description
PME_TO_Ack message does not arrive in a timely
fashion. The PCI Specification recommends a system
timeout be implemented in the 1mS to 10mS range.
pm_enter_l2_ack delay should be significantly less than
the system timeout (system dependent).
pm_l2_exit Output Set to 1 by the core for 1 clock when the core exits the L2
link state back to L0; 0 otherwise. The core exits L2
under system control or in response to a user PME
request via pm_d3cold_n_pme_assert assertion. This
output is only asserted if the core remained powered
and clocked while in L2.
pm_l2_store[2:0] Output This port contains Configuration Register information
that must be maintained through D3cold (power and
clock removed from core):

Bit[2] – AUX_Power_PM_Enable

Bit[1] – PME_Status

Bit[0] – PME_En
If the user indicates a need (via mgmt_cfg_control) for
Auxiliary Power or the ability to assert PME from
D3cold then the contents of pm_l2_store must be saved
when pm_enter_l2 is asserted and subsequently placed
onto pm_d3cold_restore when power is restored
(exiting D3cold).
If PME_En == 1 then the user may use Beacon/WAKE#
to wake the link. If PME_En == 0, then Beacon/WAKE#
may not be asserted by the user in any .
pm_d3cold_exit Input Asserted to signal an exit from D3cold (main power
removed) to D0 (main power restored) so that the core
can restore state information saved by the user in
D3cold.
pm_d3cold_exit must be asserted only when main
power is restored and prior to main power having been
being removed, pm_l2_enter was asserted without a
corresponding pm_l2_exit (core was in L2 when power
was removed).
pm_d3_cold_exit is set to 1 and held at 1 until
pm_d3_cold_exit_ack is asserted at which time
pm_d3_cold_exit must de-assert to 0 within 64 core
clocks (the 64 clocks are to allow the user design time to
perform clock synchronization between the core and
auxiliary power clock domains).
When pm_d3_cold_exit ==1, pm_d3cold_restore must
contain the value saved on pm_l2_store when
pm_l2_enter was last set prior to power removal. Also
when pm_d3_cold_exit ==1, pm_d3cold_pme_asserted