Achronix Speedster22i PCIe - Manual (Page 49)

UG030, April 26, 2013 49
Field Name Default Values Description Verilog Parameter
CfgX register to complete the
BAR as a 64-bit register[63:0].
Bit[3] is set to indicate the BAR is
prefetchable. Bits [63:4] are set to
determine the size of the BAR.
The minimum BAR size is 16
bytes, although a minimum of 4K
bytes is recommended. To
determine the BAR size, bits are
set consecutively from bit 63
down to the last desired address
bit to implement. The remaining
bits are all set to zero. For
example a 64Kbyte, prefetchable,
64-bit Memory BAR is created by
setting Base Address CfgX =
0xFFFF000C and Base Address
Cfg(X+1) to 0xFFFFFFFF to create
a 64-bit BAR with value
0xFFFFFFFFFFFF000C. For
example a 1Gbyte, prefetchable,
64-bit Memory BAR is created by
setting Base Address CfgX =
0xC000000C and Base Address
Cfg(X+1) to 0xFFFFFFFF to create
a 64-bit BAR with value
0xFFFFFFFFC000000C.
Expansion
ROM
Enable Off Off, On Determines whether an
Expansion ROM Base Address
Register is implemented, and if
so, its size. Bits [31:11] are set to
determine the size of the BAR.
Bits[10:0] must be 0 to make the
minimum BAR size 2K bytes. To
determine the Expansion ROM
BAR size, bits are set
consecutively from bit 31 down to
the last desired address bit to
implement. The remaining bits
are all set to zero. For example a
64Kbyte Expansion ROM BAR is
created by setting Expansion
ROM Cfg = 0xFFFF0000. The
Expansion ROM BAR is used to
store device specific initialization
or boot instructions that must CFG_CONSTANTS_EXP
ANSION_ROM_CFG
If Off, 0x00000000, else
=Base Address
Expansion
ROM Base
Address 0xFFFFF
800
Expansion
ROM Size 2K 2K-16M