Achronix Speedster22i PCIe - Manual (Page 43)

UG030, April 26, 2013 43
Pin Name Direction Clock Description
must be 1 if the user asserted WAKE# or generated a
Beacon to wake-up the system while in D3cold and is 0
otherwise.
pm_d3cold_exit_ack Output Set to 1 for 1 clock to acknowledge pm_d3cold_exit == 1;
0 otherwise. When pm_d3cold_exit_ack == 1, the value
on pm_d3cold_restore is used to restore Configuration
Registers values that must be saved through D3cold and
the value on pm_d3cold_pme_asserted is used to set the
PME_Status Configuration Register and send a
PM_PME message if the PME_En configuration register
is set.
pm_d3cold_restore Input See pm_d3cold_exit above.
pm_d3cold_pme_asserted Input See pm_d3cold_exit above.
pm_d3cold_n_pme_assert Input When the core is in any power state other than D3cold
(D0, D1, D2, D3hot), this port may be used to transmit a
PME message to the system to request that the system
raise the core to a lower D power level (D1 -> D0 for
example). If the core is in L2 and is configured for
Endpoint training (Upstream Lanes) and
pm_d3cold_n_pme_assert is asserted, then the core will
de-assert the PHYs TX electrical idle signal to cause the
PHY to transmit a Beacon (as per PIPE Specification)
and wait for the remote device to exit electrical idle
before retraining the link and transmitting the PME
message. Note that all exit conditions from L2 result in
the Physical & Data Link Layers going down which
resets the Data Link & Transaction Layers.
Set for one clock to cause the core to set PME_Status and
transmit a PME message (if PME_En == 1) when the core
is in any state other than D3cold; 0 otherwise. This port
may not be asserted when the core is in D3cold.
This port may only be asserted from power states that
the user is advertising the ability to assert PME from via
mgmt_cfg_control.
Configuration Register Expansion Interface
Table 9: Configuration Register Expansion Interface Port Descriptions
Pin Name Direction Clock Description