Achronix Speedster22i PCIe - Manual (Page 53)

UG030, April 26, 2013 53
Field Name Default Values Description Verilog Parameter

01 - L0s supported

10 – L1 supported

11 – L0s and L1
supported
2’b11 = Yes
2’b01 = No
Also:
CFG_CONSTANTS_ENA
BLE_L1S_POWER_MGM
T
And
CFG_CONSTANTS_ENA
BLE_L1_POWER_MGMT
Should be set to 1 if yes.
L1 Entry
Time 0x0000 0x0000-
0xFFFF Enable ASPM L1 Power Mgmt:
Set to enable the core’s ASPM L1
power management functions.
Clear to disable. This bit should
be clear for PHYs which cannot
support power management due
to missing PCI Express features
such as Electrical Idle Detection
and Generation. If this bit is set,
then ASPM L1 functionality is
implemented and may or may
not be enabled and used by
system software. If ASPM L1
support is enabled, then
mgmt_cfg_constants: ASPM L1
Entry Time specifies the ASPM L1
idle entry time. If ASPM L1
support is advertised in
mgmt_cfg_control: Active State
Power Management (ASPM)
Support in PCIe Link
Capabilities, then Enable ASPM
L1 Power Management must be 1. CFG_CONSTANTS_ASP
M_L1S_TX_ENTRY_TIM
E
Endpoint L1
Acceptable
Latency Maximu
m of 1us Endpoint L1 Acceptable Latency
– From PCI Express Base
Specification, Rev 2.1 section
7.8.3: “This field indicates the
acceptable latency that an
Endpoint can withstand due to
the transition from L1 state to the
L0 state. It is essentially an
indirect measure of the
Endpoint’s internal buffering.
Power management software
uses the reported L1 Acceptable
Latency number to compare CFG_CONTROL_PCIE_D
EV_CAP_ENDPOINT_L1
_ACCEPTABLE_LATEN
CY