Achronix Speedster22i PCIe - Manual (Page 57)

UG030, April 26, 2013 57
Field Name Default Values Description Verilog Parameter
Setting this bit is required by
PCIe Specification for Endpoints
which issue requests on their own
behalf so 1 is the recommended
value.
Completion
Timeout
Range 50us to
50ms 50us to
10ms, 10ms
to 250ms,
250ms to 4s,
4s to 64s Each bit is set to indicate whether
the user supports a particular
range of completion timeouts:

0000 – Programming not
supported; completion
timeout is in range 50uS
to 50mS

xxx1 – 50 uS to 10 mS
supported

xx1x – 10 mS to 250 mS
supported

x1xx – 250 mS to 4 s
supported

1xxx – 4s to 64 s
supported
Ex: 0110 indicates support for
both 10mS to 250 mS and 250 ms
to 4s
Devices are not required to
support several timeout ranges.
0000 is the recommended value.
CFG_CONTROL_PCIE_D
EV_CAP2_CPL_TIMEOU
T_RANGES_SUPPORTE
D
AER Version
0x2 Enable Yes Yes, No AER Version 0x2 Enable

1 == Implement AER to
version 0x2 (PCIe 2.1 and
later Specification revisions)
o Correctable Errors:
Corrected Internal
Error & Header Log
Overflow are enabled
o Uncorrectable Error:
Uncorrected Internal
Error is enabled

0 == Implement AER to
version 0x1 (PCIe 2.0 and
earlier Specification revisions)
o Correctable Errors:
Corrected Internal
Error & Header Log
Overflow are hidden
and cannot be
CFG_CONTROL_AER_V
ERSION_0X2_ENABLE