Achronix Speedster22i PCIe - Manual (Page 27)

UG030, April 26, 2013 27
Port Name Direction Clock Description
functionality.
PCI Express Packets are integer multiples of
32-bits in length. Thus, 64-bit and 128-bit Core
Data Width cores may have an unused
remainder portion in the final data word of a
packet. The core uses the packet TLP header
(Length, TLP Digest, and Format and Type) to
detect whether the packet has an unused
remainder and will automatically discard and
not transmit the unused portion of the final
data word.
bypass_tx_data_valid[15:0] Input bypass_clk DMA Bypass Tx Data Byte Valid
bypass_tx_np_ok Output bypass_clk vc0_tx_np_ok indicates when the user is
allowed to transmit non-posted requests.
1: Non-Posted Requests are permitted
0: Non-Posted Requests are not permitted
If a non-posted request is transmitted when
there are no non-posted receive buffer credits
available in the remote PCI Express device,
then the core will be unable to send the non-
posted request until credits are freed. If the
remote device is unable to free non-posted
credits until receiving a TLP from the core then
this leads to a deadlock condition that cannot
be resolved.
vc0_tx_np_ok is implemented to avoid this
condition by making it not possible for
transmissions to be stalled by the inability to
transmit non-posted requests. The core
implements a small non-posted request FIFO.
When non-posted requests cannot be accepted
by the remote device, this FIFO will fill, and
when it’s almost full threshold is hit,
vc0_tx_np_ok will de-assert (== 0) stopping the
user from being able to transmit additional
non-posted requests. Additional posted
requests and completions are not blocked by
vc0_tx_np_ok and continue to transmit if
credits are available in the remote Receive
Buffer. Per PCI Express transaction ordering
rules, Posted Requests and Completions must
be allowed to pass Non-Posted requests to
avoid deadlocks; Completions and Posted
Requests are not required to be able to pass
one another.