Achronix Speedster22i PCIe - Manual (Page 19)

UG030, April 26, 2013 19

Bit[2] – Addressable FIFO DMA – If set to 1, the DMA Back-
End will use the same Card Starting Address for all DMA
Interface transactions for this Descriptor; this bit must be set
the same for all Descriptors that are part of the same packet
transfer; Addressable FIFO AXI addresses must be chosen
by the user design such that they are aligned to AXI max
burst size * AXI data width address boundaries; For
example: 16 * 16 == 256 bytes for AXI3 max burst size == 16
and AXI_DATA_WIDTH == 128-bits == 16 bytes

Bit[1] – IRQOnError – Set to generate an interrupt when this
Descriptor Completes with error; clear to not generate an
interrupt when this Descriptor Completes with error

Bit[0] – IRQOnCompletion – Set to generate an interrupt
when this Descriptor Completes without error; clear to not
generate an interrupt when this Descriptor Completes
without error

S2CDescStatusFlags[7:0] - Status
• Bits[7:5] – Reserved
• Bit 4 – Error – Set when the Descriptor completes due to an
error; clear otherwise
• Bits[3:2] - Reserved
• Bit 1 – Short – Set when the Descriptor completed with a
byte count less than the requested byte count; clear
otherwise; this is generally an error for S2C Packet DMA
since packets are normally not truncated by the user design.
• Bit 0 – Complete – Set when the Descriptor completes
without an error; clear otherwise

S2CDescStatusErrorFlags[3:0] – Status – Additional information as
to why S2CDescStatusFlags[4] == Error is set. If
S2CDescStatusFlags[4] == Error is set then one or more of the
following bits will be set to indicate the additional error source
information.
• Bit 3 – Reserved
• Bit 2 – Set when received one or more DMA read data
completions with ECRC Errors
• Bit 1 – Set when received one or more DMA read data
completions marked as Poisoned (EP == 1)
• Bit 0 – Set when received one or more DMA read data
completions with Unsuccessful Completion Status

S2CDescUserControl[63:0] – Control
• Contains application specific control information to pass
from software to the user hardware design; the DMA Engine
provides the value of S2CDescUserControl to the user
design the same clock that SOP is provided.
S2CDescUserControl is not used by the DMA Engine and is
purely for application specific needs. Use of
S2CDescUserControl is optional.

S2CDescByteCount[19:0] – Control & Status