Achronix Speedster22i PCIe - Manual (Page 76)

UG030, April 26, 2013 76
///// MASTER SIDE INTERFACE ////
input m_aclk
;
input m_areset_n ;
input m_awvalid ;
input [15:0] m_awaddr ;
input m_wvalid ;
input [31:0] m_wdata ;
input [3:0] m_wstrb ;
input m_bready ;
input m_arvalid ;
input [15:0] m_araddr ;
input m_rready ;
/////// TARGET SIDE INTERFACE //////
input t_areset_n
;
input t_aclk ;
input t_awready ;
input t_wready ;
input t_bvalid ;
input [1:0] t_bresp ;
input t_arready ;
input t_rvalid ;
input [127:0] t_rdata ;
input [1:0] t_rresp ;
input t_rlast ;
///// MANAGEMENT INTERFACE ////
input mgmt_transactions_pending
;
input user_interrupt ;
input pm_l2_enter_ack ;
input pm_d3cold_exit ;
input [2:0] pm_d3cold_restore ;
input pm_d3cold_pme_asserted ;
input pm_d3cold_n_pme_assert ;
///// CONFIGURATION SIDE ////
input [11:2] core_cfg_exp_addr
;
input core_cfg_exp_wr_en ;
input [31:0] core_cfg_exp_wr_data ;
input [3:0] core_cfg_exp_wr_be ;
input core_cfg_exp_rd_en ;
///// OUTPUTS ////