Achronix Speedster22i PCIe - Manual (Page 51)

UG030, April 26, 2013 51
Field Name Default Values Description Verilog Parameter
PHY receiver uses the FTS sets to
recover symbol lock. NFTS
should be chosen in accordance
with the required time for the PCI
Express PHY which is being used
with the core to achieve symbol
lock when exiting Electrical Idle
from L0s and should also take
into account the PHY RX_IDLE to
RX_DATA latency. Valid values
are 0x00 and 0x10 to 0xFF (0x01 to
0x0F are not permitted). 0x00 is a
special case and selects the
maximum value or 0xFF. Lower
values may only be used by PHY
with low RX_IDLE to RX_DATA
latency. See NFTS Timeout
Extend for additional detail.
L0s Tx Entry
Time 0x0000 0x0000-
0xFFFF ASPM L0s TX Entry Time –
Number of nanoseconds of idle
time to wait before entering L0s
TX. Idle time is defined as no TLP
or DLLP transmission pending or
actively being transmitted. By
PCIe Specification, the value
programmed should be <= 7 uS
(0x1B58). Too low a value risks
wasting link bandwidth due to
L0s entry/exit latencies. Too high
a value will reduce L0s power
savings. Only used if Enable L0s
Power Mgmt is set. 0 is a special
case and selects 6.9 uS (0x1AF4). CFG_CONSTANTS_ASP
M_L0S_TX_ENTRY_TIM
E
Endpoint
L0s
Acceptable
Latency 64ns 64ns, 128ns,
256ns, 512ns,
1us, 2us,
4us, No limit Endpoint L0s Acceptable Latency
– From PCI Express Base
Specification, Rev 2.1 section
7.8.3: “Acceptable total latency
that an Endpoint can withstand
due to the transition from L0s
state to the L0 state. It is
essentially an indirect measure of
the Endpoint’s internal buffering.
Power management software
uses the reported L0s Acceptable
Latency number to compare
against the L0s exit latencies CFG_CONTROL_PCIE_D
EV_CAP_ENDPOINT_L0
S_ACCEPTABLE_LATEN
CY