Achronix Speedster22i PCIe - Manual (Page 60)

UG030, April 26, 2013 60
Field Name Default Values Description Verilog Parameter
value, and 32-bit Vector Control
field, so a 32 Interrupt Vector
MSI-X Table requires a 512 (32 *
16) byte table.
MSI-X Table
BAR
indicator BAR0 BAR0,
BAR1, BAR2 MSI-X Table BIR[2:0] – Value to
place into MSI-X Capability :
Table BIR field.
MSI-X functionality requires the
user design to implement the
MSI-X Table in Memory Space
mapped by 1 (32-bit) or 2 (64-bit)
Memory Base Address Registers.
MSI-X Table BIR and MSI-X Table
Offset indicate to system software
where the MSI-X Table is located.
Software writes and reads to the
MSI-X Table and MSI-X PBA are
handled by the user hardware
design. When a MSI-X interrupt is
desired to be generated, the user
hardware design passes the core a
single MSI-X Table entry
corresponding to the desired
interrupt vector. The core uses
this information to create a MSI-X
write request (Memory Write
Request) packet.
MSI-X functionality is described
in the PCI Local Bus Specification,
Rev. 3.0. The specification
recommends mapping the MSI-X
Table and MSI-X PBA into
separate, dedicated Base Address
Registers. If this is not possible
then it is recommended to map
the MSI-X Table and MSI-X PBA
into the same dedicated Base
Address Register. If this is not
possible then the MSI-X Table
and MSI-X PBA may be mapped
into a Memory Base Address
Register that is shared with other
functions. If the MSI-X Table and
MSI-X PBA are mapped into a
Base Address Register that is
shared with other functions, then CFG_CONTROL_MSI_X_
TABLE_BIR