Toshiba – Toshiba TMP87CP24AF User Manual

Page 19

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TOSHIBA

TMP87CM24A/P24A

(2) Dual-dock mode

Both

high-frequency

and

low-frequency

oscillation

circuits

are

used

in

this

mode.

Pins

P21

(XTIN)

and

P22

(XTOUT)

cannot

be

used

as

input/output

ports.

The

main

system

clock

is

obtained

from

the

high-frequency

clock

in

NORMAL2

and

IDLE2

modes,

and

is

obtained

from

the

low-frequency

clock

in SLOW and SLEEP modes. The machine cycle time is 4/fc [s] (0.5 fjs at fc =

8

MHz) in NORMAL2 and

IDLE2 modes, and 4/fs [s] (122 fxs at fs = 32.768 kHz) in SLOW and SLEEP modes. Note that the

TMP87PP24

is

placed

in

the

single-clock

mode

during

reset. To use the dual-clock mode, the low-

frequency oscillator should be turned on by executing [SET (SYSCR2).XTEN] instruction.

© NORMAL2mode

In

this

mode,

the

CPU

core

operates

using

the

high-frequency

clock.

On-chip

peripherals

operate

using

the

high-frequency

clock

and/or

low-frequency

clock.

In

case

that

the

dual­

clock

mode

has

been

selected

by

an

option,

the

TMP87CM24A/P24A

are

placed

in

this

mode

after reset.

@ SLOW mode

This

mode

can

be

used

to

reduce

power-consumption

by

turning

off

oscillation

of

the

high-

frequency

clock.

The

CPU

core

and

on-chip

peripherals

operate

using

the

low-frequency

clock.

Switching

back

and

forth

between

NORMAL2

and

SLOW

modes

is

performed

by

the

system

control register

2

.

(3)

IDLE2mode

In

this

mode,

the

internal

oscillation

circuits

remain

active.

The

CPU

and

the

watchdog

timer

are

halted;

however,

on-chip

peripherals

remain

active

(operate

using

the

high-frequency

clock

and/or

the

low-frequency

clock).

Starting

and

releasing

of

IDLE2

mode

are

the

same

as

for IDLE1 mode, except that operation returns to NORMAL2 mode.

® SLEEP mode

In

this

mode,

the

internal

oscillation

circuit

of

the

low-frequency

clock

remains

active.

The

CPU,

the

watchdog

timer,

and

the

internal

oscillation

circuit

of

the

high-frequency

clock

are

halted;

however,

on-chip

peripherals

remain

active

(operate

using

the

low-frequency

clock).

Starting

and

releasing

of

SLEEP

mode

is

the

same

as

for

IDLE1

mode,

except

that

operation

returns to SLOW mode.

(D STOP2 mode

As in STOP1 mode, all system operations are halted in this mode.

3

-

24-19

2002

-

10-03

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